diff options
| author | Bitan Biswas <bbiswas@nvidia.com> | 2011-12-08 12:33:15 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2011-12-15 11:53:19 +0530 |
| commit | 8632f4ecc6f40e1aaae75c138835ee0954758b14 (patch) | |
| tree | f0dad63352d47171336e318cf96932fdcbdd398d /arch/arm/mach-tegra/pm-irq.c | |
| parent | 85c0a5384debd436911fbed118ce804c217d1019 (diff) | |
arm: tegra: irq: PMC WAKE2 level configuration
Wake level was not getting programmed for wake sources beyond WAKE31.
Previous expression was using 32-bit operation. Changing constant 1
to 1ull corrects the calculation.
bug 907980
Change-Id: Ie2e5f9a7dd4024db9d96859251169027570540f0
Reviewed-on: http://git-master/r/68907
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm-irq.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm-irq.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/pm-irq.c b/arch/arm/mach-tegra/pm-irq.c index 79b0b1a4cbeb..63e3e6c8d72b 100644 --- a/arch/arm/mach-tegra/pm-irq.c +++ b/arch/arm/mach-tegra/pm-irq.c @@ -99,8 +99,11 @@ static inline u64 read_pmc_wake_level(void) static inline void write_pmc_wake_level(u64 value) { + pr_info("Wake[31-0] level=0x%x\n", (u32)(value & 0xFFFFFFFF)); writel((u32)value, pmc + PMC_WAKE_LEVEL); #ifndef CONFIG_ARCH_TEGRA_2x_SOC + pr_info("Tegra3 wake[63-32] level=0x%x\n", (u32)((value >> 32) & + 0xFFFFFFFF)); __raw_writel((u32)(value >> 32), pmc + PMC_WAKE2_LEVEL); #endif } @@ -179,17 +182,17 @@ int tegra_pm_irq_set_wake_type(int irq, int flow_type) switch (flow_type) { case IRQF_TRIGGER_FALLING: case IRQF_TRIGGER_LOW: - tegra_lp0_wake_level &= ~(1 << wake); - tegra_lp0_wake_level_any &= ~(1 << wake); + tegra_lp0_wake_level &= ~(1ull << wake); + tegra_lp0_wake_level_any &= ~(1ull << wake); break; case IRQF_TRIGGER_HIGH: case IRQF_TRIGGER_RISING: - tegra_lp0_wake_level |= 1 << wake; - tegra_lp0_wake_level_any &= ~(1 << wake); + tegra_lp0_wake_level |= (1ull << wake); + tegra_lp0_wake_level_any &= ~(1ull << wake); break; case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING: - tegra_lp0_wake_level_any |= 1 << wake; + tegra_lp0_wake_level_any |= (1ull << wake); break; default: return -EINVAL; |