diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-09-14 22:27:07 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:41 -0800 |
| commit | d0319f29ce8f449a8f68062c4066fc6cf7f84f8d (patch) | |
| tree | 3979f1506200de6bf071ed6efdc2a586d46ad1f9 /arch/arm/mach-tegra/pm-t3.c | |
| parent | 3ff036710d4b1bd74f9cbacb49a87851932e77da (diff) | |
ARM: tegra: power: Restore Tegra3 MC registers after LP0
On exit from deep sleep (LP0) restore from SDRAM Tegra3 MC registers
that are not saved in PMC scratch file for boot-rom restoration. Since
SDRAM after LP0 is running at boot rate, MC registers are saved only
once during initialization.
Bug 874351
(ported from commit 99966c242920978a92f3f51e5957ada30afc4b1d)
Change-Id: I9bf06ddb83fa6435a4f5bd29ec58bb195a189678
Reviewed-on: http://git-master/r/61045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R272136c877818d44b0cf28f8b5f720af71623301
Diffstat (limited to 'arch/arm/mach-tegra/pm-t3.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm-t3.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index 5d55a9e2111f..f82535f4a601 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -369,21 +369,17 @@ int tegra_cluster_control(unsigned int us, unsigned int flags) #endif #ifdef CONFIG_PM_SLEEP -static u32 mc_reserved_rsv; -static u32 mc_emem_arb_override; void tegra_lp0_suspend_mc(void) { - void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE); - mc_reserved_rsv = readl(mc + MC_RESERVED_RSV); - mc_emem_arb_override = readl(mc + MC_EMEM_ARB_OVERRIDE); + /* Since memory frequency after LP0 is restored to boot rate + mc timing is saved during init, not on entry to LP0. Keep + this hook just in case, anyway */ } void tegra_lp0_resume_mc(void) { - void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE); - writel(mc_reserved_rsv, mc + MC_RESERVED_RSV); - writel(mc_emem_arb_override, mc + MC_EMEM_ARB_OVERRIDE); + tegra_mc_timing_restore(); } void tegra_lp0_cpu_mode(bool enter) |