diff options
| author | Bo Yan <byan@nvidia.com> | 2012-10-08 19:52:49 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:38:38 -0700 |
| commit | 63c52211c20d6ce2adad9d4f19968f924e5cf3fb (patch) | |
| tree | 33bd14d5faedf7bef6499da21e3483d27c58dc2e /arch/arm/mach-tegra/pm-t3.c | |
| parent | e911ae07fea6333bae8ae9e4ff9ee8d908e05182 (diff) | |
ARM: tegra11x: CPU start up fix
The first time when a CPU powers up in kernel, it has to be
done by directly toggling PMC register.
Subsequent CPU power up sequence is controlled by flow controller.
This is done after LP0 exit as well.
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/143296
Change-Id: If32712706d827e4d0337d75163449cfa0a3a50f8
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146484
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Rebase-Id: R8909dae486432fd628e8d89735634eee26063f4e
Diffstat (limited to 'arch/arm/mach-tegra/pm-t3.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm-t3.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index 8df17f491706..b62701f66034 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -142,6 +142,7 @@ static int cluster_switch_prolog_clock(unsigned int flags) writel(SuperCclkDivier, CAR_SUPER_CCLKG_DIVIDER); } +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) /* Hold G CPUs 1-3 in reset after the switch */ reg = CPU_RESET(1) | CPU_RESET(2) | CPU_RESET(3); writel(reg, CAR_RST_CPUG_CMPLX_SET); @@ -161,6 +162,7 @@ static int cluster_switch_prolog_clock(unsigned int flags) /* Enable the G CPU complex clock after the switch */ reg = CAR_CLK_ENB_V_CPU_G; writel(reg, CAR_CLK_ENB_V_SET); +#endif } /* Switching to LP? */ else if (flags & TEGRA_POWER_CLUSTER_LP) { @@ -180,6 +182,7 @@ static int cluster_switch_prolog_clock(unsigned int flags) writel(SuperCclkDivier, CAR_SUPER_CCLKLP_DIVIDER); } +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) /* Take the LP CPU ut of reset after the switch */ reg = CPU_RESET(0); writel(reg, CAR_RST_CPULP_CMPLX_CLR); @@ -191,6 +194,7 @@ static int cluster_switch_prolog_clock(unsigned int flags) /* Enable the LP CPU complex clock after the switch */ reg = CAR_CLK_ENB_V_CPU_LP; writel(reg, CAR_CLK_ENB_V_SET); +#endif } return 0; |