diff options
| author | Bo Yan <byan@nvidia.com> | 2012-05-07 14:24:20 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:11:14 -0700 |
| commit | c911d2ea1e1ce35b87e06c1d7954560577732f75 (patch) | |
| tree | d108be9d5ca60fbb10613f1ba243e86ec6bbebed /arch/arm/mach-tegra/pm-t3.c | |
| parent | 6d65d5bb0f0a20e9930de90b04a76ba5f7130ee9 (diff) | |
ARM: tegra11: CPU rail power up sequence
It is necessary to disable RAM repair bypass when CPU rail is
powered up. This needs to be done even in case of HW controlled
CPU rail power-on.
This change also enables cluster switch to use "power_gate" flag
defined in sysfs to control the power gating mode. For LP0 entry
case, rail-gating is set to default.
Set default power gating mode for cluster switch to rail gating.
For chips that doesn't support symmetric power gating, "0" is
the default value which will trigger rail-gating.
Change-Id: Ia7ccb023118bbfba4fa53dc263bdfda59e29f089
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/101045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R50b64bfc236a664028edc822219af0d30d1af043
Diffstat (limited to 'arch/arm/mach-tegra/pm-t3.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm-t3.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index 595e405a2686..700ab965d19d 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -211,6 +211,14 @@ void tegra_cluster_switch_prolog(unsigned int flags) if (!target_cluster) goto done; +#if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE) + reg &= ~FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK; + if (flags & TEGRA_POWER_CLUSTER_PART_CRAIL) + reg |= FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL; + if (flags & TEGRA_POWER_CLUSTER_PART_NONCPU) + reg |= FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU; +#endif + if ((current_cluster != target_cluster) || (flags & TEGRA_POWER_CLUSTER_FORCE)) { if (current_cluster != target_cluster) { @@ -296,6 +304,9 @@ void tegra_cluster_switch_epilog(unsigned int flags) reg = readl(FLOW_CTRL_CPU_CSR(0)); reg &= ~(FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE | FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER); +#if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE) + reg &= ~FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK; +#endif writel(reg, FLOW_CTRL_CPU_CSR(0)); /* Perform post-switch LP=>G clean-up */ @@ -359,10 +370,22 @@ int tegra_cluster_control(unsigned int us, unsigned int flags) if (target_cluster == TEGRA_POWER_CLUSTER_G) { s64 t = ktime_to_us(ktime_sub(now, last_g2lp)); s64 t_off = tegra_cpu_power_off_time(); +#if defined(CONFIG_ARCH_TEGRA_11x_SOC) + u32 reg; +#endif if (t_off > t) udelay((unsigned int)(t_off - t)); tegra_dvfs_rail_on(tegra_cpu_rail, now); +#if defined(CONFIG_ARCH_TEGRA_11x_SOC) + reg = readl(FLOW_CTRL_RAM_REPAIR); + reg &= ~FLOW_CTRL_RAM_REPAIR_BYPASS_EN; + writel(reg, FLOW_CTRL_RAM_REPAIR); + /* power up C rail */ + reg = readl(FLOW_CTRL_CPU_PWR_CSR); + reg |= FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE; + writel(reg, FLOW_CTRL_CPU_PWR_CSR); +#endif } else { last_g2lp = now; @@ -428,6 +451,9 @@ void tegra_lp0_cpu_mode(bool enter) if (entered_on_g) { flags = enter ? TEGRA_POWER_CLUSTER_LP : TEGRA_POWER_CLUSTER_G; flags |= TEGRA_POWER_CLUSTER_IMMEDIATE; +#if defined(CONFIG_ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE) + flags |= TEGRA_POWER_CLUSTER_PART_DEFAULT; +#endif tegra_cluster_control(0, flags); pr_info("Tegra: switched to %s cluster\n", enter ? "LP" : "G"); } |