diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2012-02-23 13:18:31 +0200 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-03-07 22:19:27 -0800 |
| commit | 64e110a41e2ac7de052d1f02b54efdd962864fdd (patch) | |
| tree | 6db4559c4bfd538204eb393925ab234bea344d9c /arch/arm/mach-tegra/pm.c | |
| parent | 65b1807ed71f72a6f3d8d47e70e4f42d9a874518 (diff) | |
ARM: tegra: Clean kernel and I/O mappings upon LP2
There is no need to flush the complete L2 upon LP2
entry but it is necessary to clean the page table
entries needed by LP2 code sequence that has L2 off
and MMU on.
Bug 931316
Change-Id: Ice353f16d35ee24d4387e7b9b135f205c4d0ba32
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/86293
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 450c5e17c2d2..ee5517e5e21d 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -577,6 +577,7 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags) { u32 mode; /* hardware + software power mode flags */ unsigned int remain; + pgd_t *pgd; /* Only the last cpu down does the final suspend steps */ mode = readl(pmc + PMC_CTRL); @@ -611,6 +612,14 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags) suspend_cpu_complex(mode); tegra_cluster_switch_time(flags, tegra_cluster_switch_time_id_prolog); flush_cache_all(); + /* + * No need to flush complete L2. Cleaning kernel and IO mappings + * is enough for the LP code sequence that has L2 disabled but + * MMU on. + */ + pgd = cpu_get_pgd(); + outer_clean_range(__pa(pgd + USER_PTRS_PER_PGD), + __pa(pgd + PTRS_PER_PGD)); outer_disable(); tegra_sleep_cpu(PLAT_PHYS_OFFSET - PAGE_OFFSET); |