diff options
| author | Pradeep Goudagunta <pgoudagunta@nvidia.com> | 2011-11-04 15:55:01 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:49 -0800 |
| commit | e1ce78dfa550f40f472e4d378295e025f3f86e57 (patch) | |
| tree | d14d33c669918c86ae991959a405791f6195e3e5 /arch/arm/mach-tegra/pm.c | |
| parent | 81d0107fd34cbe6f02de55ca5dfd5531771e9ea5 (diff) | |
ARM: tegra: uart: Restore FCR in uart resume
Restore FCR while resuming debug uart, to enable RX and TX FIFOs with
trigger levels configured during initialisation of debug uart port.
Bug 867063
Change-Id: I9665ff29a53c3e2e6c78a3037e20e7362a642f77
Reviewed-on: http://git-master/r/62411
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Ra3b9858456b952ab539a36019a55863077094054
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index e359a273dad6..f43954d5a9d5 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -1128,6 +1128,9 @@ static void tegra_debug_uart_resume(void) /* DLAB = 0 */ writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4); + writeb(UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_01 | UART_FCR_R_TRIG_01, + uart + UART_FCR * 4); + writeb(tegra_sctx.uart[2], uart + UART_IER * 4); /* DLAB = 1 */ |