diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-03-13 00:41:14 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:27 -0800 |
| commit | 4f325a029dc651dd924002a456b039a7bc00385b (patch) | |
| tree | fc46cbc51917b61184ba5392446916ef04423336 /arch/arm/mach-tegra/pm.h | |
| parent | e630c3d716c0a883995c0b7a2938c35d5de25b72 (diff) | |
ARM: tegra: clock: Re-factor Tegra3 cpu clocks
Added second level virtualization (on top of virtual cpu rate control)
to support different Tegra3 CPU power modes: low power (LP) mode and
geared performance (G) mode. Virtual cpu complex (cpu_cmplx) clock is
defined as a child with two parents: virtual cpu_lp and virtual cpu_g
clocks for the respective modes. Mode switch sequence was integrated
into cpu_cmplx set parent implementation. (Before this commit mode
switch was triggered outside the clock framework, which created cpu
clock/mode synchronization problems).
Each mode clock is derived from its own super clock mux (cclk_lp and
cclk_g) to statically match Tegra3 h/w layout. (Before this commit the
code had to dynamically synchronize CPU mode and active mux selection).
This change also allowed to support PLLX output divider for low power
mode as fixed 1:2 divider with bypass control embedded into cclk_lp
parent section.
Updated auto and sysfs CPU mode switch calls to use new clock framework,
and removed clock manipulation from the low level mode switch
implementation.
Original-Change-Id: Ibc3cc495b2ff29e2d3417eff2bfd45535cbd015b
Reviewed-on: http://git-master/r/24734
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I23ae80edbf14fb22727a6fc317cd9e5baf8bd6be
Rebase-Id: Rdcd4a2165ebd92bf4caa35d68ca81d19a3789351
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index b03a0f4b39d4..88a3f8fe29e0 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -100,6 +100,7 @@ void tegra_idle_lp2_last(unsigned int flags); #ifdef CONFIG_ARCH_TEGRA_2x_SOC #define INSTRUMENT_CLUSTER_SWITCH 0 /* Must be zero for ARCH_TEGRA_2x_SOC */ #define DEBUG_CLUSTER_SWITCH 0 /* Must be zero for ARCH_TEGRA_2x_SOC */ +#define PARAMETERIZE_CLUSTER_SWITCH 0 /* Must be zero for ARCH_TEGRA_2x_SOC */ static inline int tegra_cluster_control(unsigned int us, unsigned int flags) { return -EPERM; } #define tegra_cluster_switch_prolog(flags) do {} while(0) @@ -108,13 +109,12 @@ static inline bool is_g_cluster_present(void) { return true; } static inline unsigned int is_lp_cluster(void) { return 0; } -static inline unsigned long tegra_get_lpcpu_max_rate(void) -{ return 0; } #define tegra_lp0_suspend_mc() do {} while(0) #define tegra_lp0_resume_mc() do {} while(0) #else #define INSTRUMENT_CLUSTER_SWITCH 1 /* Should be zero for shipping code */ #define DEBUG_CLUSTER_SWITCH 1 /* Should be zero for shipping code */ +#define PARAMETERIZE_CLUSTER_SWITCH 1 /* Should be zero for shipping code */ int tegra_cluster_control(unsigned int us, unsigned int flags); void tegra_cluster_switch_prolog(unsigned int flags); void tegra_cluster_switch_epilog(unsigned int flags); @@ -131,7 +131,6 @@ static inline unsigned int is_lp_cluster(void) reg = readl(FLOW_CTRL_CLUSTER_CONTROL); return (reg & 1); /* 0 == G, 1 == LP*/ } -unsigned long tegra_get_lpcpu_max_rate(void); void tegra_lp0_suspend_mc(void); void tegra_lp0_resume_mc(void); #endif @@ -142,6 +141,13 @@ extern unsigned int tegra_cluster_debug; #else #define DEBUG_CLUSTER(x) do { } while (0) #endif +#if PARAMETERIZE_CLUSTER_SWITCH +void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags); +#else +static inline void tegra_cluster_switch_set_parameters( + unsigned int us, unsigned int flags) +{ } +#endif static inline void flowctrl_writel(unsigned long val, void __iomem *addr) { |