diff options
| author | Bo Yan <byan@nvidia.com> | 2012-05-07 14:24:20 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:11:14 -0700 |
| commit | c911d2ea1e1ce35b87e06c1d7954560577732f75 (patch) | |
| tree | d108be9d5ca60fbb10613f1ba243e86ec6bbebed /arch/arm/mach-tegra/pm.h | |
| parent | 6d65d5bb0f0a20e9930de90b04a76ba5f7130ee9 (diff) | |
ARM: tegra11: CPU rail power up sequence
It is necessary to disable RAM repair bypass when CPU rail is
powered up. This needs to be done even in case of HW controlled
CPU rail power-on.
This change also enables cluster switch to use "power_gate" flag
defined in sysfs to control the power gating mode. For LP0 entry
case, rail-gating is set to default.
Set default power gating mode for cluster switch to rail gating.
For chips that doesn't support symmetric power gating, "0" is
the default value which will trigger rail-gating.
Change-Id: Ia7ccb023118bbfba4fa53dc263bdfda59e29f089
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/101045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R50b64bfc236a664028edc822219af0d30d1af043
Diffstat (limited to 'arch/arm/mach-tegra/pm.h')
| -rw-r--r-- | arch/arm/mach-tegra/pm.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index fe685d439065..a5b7ce7ef9b2 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -84,9 +84,22 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags); #define FLOW_CTRL_CLUSTER_CONTROL \ (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c) +#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL (1<<13) +#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU (1<<12) +#define FLOW_CTRL_CPU_CSR_ENABLE_EXT_MASK ( \ + FLOW_CTRL_CPU_CSR_ENABLE_EXT_NCPU | \ + FLOW_CTRL_CPU_CSR_ENABLE_EXT_CRAIL ) #define FLOW_CTRL_CPU_CSR_IMMEDIATE_WAKE (1<<3) #define FLOW_CTRL_CPU_CSR_SWITCH_CLUSTER (1<<2) +#define FLOW_CTRL_CPU_PWR_CSR \ + (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x38) +#define FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE 1 + +#define FLOW_CTRL_RAM_REPAIR \ + (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x40) +#define FLOW_CTRL_RAM_REPAIR_BYPASS_EN (1<<2) + #define FUSE_SKU_DIRECT_CONFIG \ (IO_ADDRESS(TEGRA_FUSE_BASE) + 0x1F4) #define FUSE_SKU_DISABLE_ALL_CPUS (1<<5) |