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authorGary King <gking@nvidia.com>2010-04-14 20:11:24 -0700
committerGary King <gking@nvidia.com>2010-04-15 20:09:05 -0700
commit69171ba958a221624ccabf08a9cde5ff03b51cf1 (patch)
tree7280a0980cc1496eeddab24ca0ba711114025198 /arch/arm/mach-tegra/power-macros.S
parent42705eb0a3d53b5c23f9ea439e97099b66320703 (diff)
[ARM] tegra: add LP2 idle-mode support
LP2 idle mode power-gates the main CPU complex, requiring a full processor state save and restore from a reset vector processor context area is allocated during platform initialization from the kernel, and mapped into the hotplug page tables (which also serve as the initial page tables for the LP2 main processor reset) restoring the processor from LP2 requires calculation of a system- and APB-clock-dependent CPU power good timer value. on Harmony, 2ms is a good baseline value for this, and the APB clock is running at 13.5MHz. these values need to be un-hardcoded for other platforms. Change-Id: I70a18a1d995e1d34da64d60fbdcd4568ef442f0c
Diffstat (limited to 'arch/arm/mach-tegra/power-macros.S')
-rw-r--r--arch/arm/mach-tegra/power-macros.S45
1 files changed, 45 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/power-macros.S b/arch/arm/mach-tegra/power-macros.S
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+/*
+ * arch/arm/mach-tegra/power-macros.S
+ *
+ * Assembly macros useful for power state save / restore routines
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+ mrc p15, 0, \rd, c0, c0, 5
+ and \rd, \rd, #0xF
+.endm
+
+/* waits until the microsecond counter (base) ticks, for exact timing loops */
+.macro wait_for_us, rd, base, tmp
+ ldr \rd, [\base]
+1001: ldr \tmp, [\base]
+ cmp \rd, \tmp
+ beq 1001b
+ mov \tmp, \rd
+.endm
+
+/* waits until the microsecond counter (base) is >= rn */
+.macro wait_until, rn, base, tmp
+1002: ldr \tmp, [\base]
+ sub \tmp, \tmp, \rn
+ ands \tmp, \tmp, #0x80000000
+ dmb
+ bne 1002b
+.endm