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| author | Scott Williams <scwilliams@nvidia.com> | 2011-08-03 21:38:01 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:02 -0800 |
| commit | e3e523668c9d6431ba5b2888707cd96b9d3f75b6 (patch) | |
| tree | 9073d7993ac99f4bc76c12c6e75ef7e0d168565e /arch/arm/mach-tegra/sleep-t2.S | |
| parent | e0047bcef58bc524b38217c7da7feca23388b839 (diff) | |
ARM: tegra: power: Use uniform save/restore register set
Modify the register usage of tegra_cpu_save so that the same set
of registers is saved to and restored from the stack.
Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t2.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t2.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index a0547084dd27..4ae200834df5 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -170,8 +170,8 @@ ENDPROC(tegra2_cpu_is_resettable_soon) * tegra2_tear_down_core in IRAM */ ENTRY(tegra2_sleep_core) - mov r3, lr @ set resume address to lr - bl tegra_cpu_save + mov r12, pc @ return here is via r12 + b tegra_cpu_save mov32 r1, tegra2_tear_down_core mov32 r2, tegra2_iram_start sub r1, r1, r2 @@ -184,9 +184,9 @@ ENDPROC(tegra2_sleep_core) * tegra2_sleep_wfi(unsigned long v2p) */ ENTRY(tegra2_sleep_wfi) - mov r3, lr @ set resume address to lr mrc p15, 0, r2, c1, c0, 1 @ save actlr before exiting coherency - bl tegra_cpu_save + mov r12, pc @ return here is via r12 + b tegra_cpu_save mov r11, r2 mov32 r3, TEGRA_PMC_VIRT |