diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-08-09 18:14:11 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:03 -0800 |
| commit | 7b6aed43ac4deef93e61e5f76d68099cf2c6540d (patch) | |
| tree | 6355ffac82d31191901394e7df950cc5176885c2 /arch/arm/mach-tegra/sleep-t2.S | |
| parent | 9f49e8468bf3cab50e0618df948b26920bd7e161 (diff) | |
ARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2
Don't try to flush the L1 D-cache for an aborted LP2 on the
secondary CPU if the L2 cache is enabled. The L1 cache will have
already been flushed and disabled by the suspend-side code.
Change-Id: If6fc7bd0f7d630e6cdcda6824411503f346c5405
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rc50e525a320986432d2b125f82f846f94f605cc3
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t2.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t2.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index 82e5ce3b7689..3144368c23f0 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -216,6 +216,7 @@ ENTRY(tegra2_sleep_wfi) bl tegra_pen_unlock +#if USE_TEGRA_CPU_SUSPEND /* Enable the data cache and SMP coherency */ mrc p15, 0, r10, c1, c0, 0 orr r10, r10, #CR_C @@ -224,6 +225,9 @@ ENTRY(tegra2_sleep_wfi) isb mcr p15, 0, r11, c1, c0, 1 @ reenable coherency +#else + mcr p15, 0, r11, c1, c0, 1 @ reenable coherency + @ the cpu was running with coherency disabled, caches may be out of date #ifdef MULTI_CACHE mov32 r10, cpu_cache @@ -232,6 +236,7 @@ ENTRY(tegra2_sleep_wfi) #else bl __cpuc_flush_kern_all #endif +#endif pop_ctx_regs r0, r1 @ restore context registers mov pc, lr |