diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-08-04 13:32:10 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:02 -0800 |
| commit | f312f55cb9bd593591432db3d4a5c1677b419a39 (patch) | |
| tree | 0d21c5fde7a594c07bd7293f51e81654dceee440 /arch/arm/mach-tegra/sleep-t2.S | |
| parent | 20e0db1694cafa07e5451b5416819da3ead119fe (diff) | |
ARM: tegra: power: Save CPU context to non-cacheable stack
The standard cpu_suspend does not work if there is an exernal
L2 cache in the system individual CPUs are suspending without
shutting down the whole CPU complex. As a workaround for this
problem, we must save the CPU context to a non-cacheable region
of memory.
Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t2.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t2.S | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index 93ae8b293a93..82e5ce3b7689 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -198,9 +198,10 @@ ENTRY(tegra2_sleep_wfi) /* * cpu may be reset while in wfi, which will return through - * tegra_resume to cpu_resume to tegra_cpu_resume + * tegra_resume to tegra_cpu_resume_phys to tegra_cpu_resume * or interrupt may wake wfi, which will return here - * cpu state is unchanged - MMU is on, cache is on, coherency is off + * cpu state is unchanged - MMU is on, cache is on, coherency + * is off, and the data cache is off * * r11 contains the original actlr */ @@ -215,6 +216,12 @@ ENTRY(tegra2_sleep_wfi) bl tegra_pen_unlock + /* Enable the data cache and SMP coherency */ + mrc p15, 0, r10, c1, c0, 0 + orr r10, r10, #CR_C + dsb + mcr p15, 0, r10, c1, c0, 0 + isb mcr p15, 0, r11, c1, c0, 1 @ reenable coherency @ the cpu was running with coherency disabled, caches may be out of date |