diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-02-11 20:19:42 -0800 |
|---|---|---|
| committer | Lokesh Pathak <lpathak@nvidia.com> | 2012-02-23 22:58:57 -0800 |
| commit | cb0428145196ed7a75861c78d28f46b6bc8d2320 (patch) | |
| tree | 9818d06016f1294a47f412c1813a3e7fe2d9e6eb /arch/arm/mach-tegra/sleep-t3.S | |
| parent | 3e39a36eb51fb4f755bf9d3229e91c3a58663b97 (diff) | |
ARM: tegra: power: Don't lower clocks on LP0 entry
Do not change (lower) CPU and system clocks, and do not disable PLLs
on entry to LP0, since all clocks and PLLs are stopped in h/w, anyway.
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 0142197cf7b1828fa7935c9d8715f37313864db1)
Change-Id: I2f175882d4d3dcfe5aee9c460f873a5e907e4ece
Reviewed-on: http://git-master/r/84714
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 4e634099d53f..5ea7334c45fb 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -513,8 +513,19 @@ tegra3_tear_down_core: * r7 = TEGRA_TMRUS_BASE */ tegra3_cpu_clk32k: + ldr r0, [r4, #PMC_CTRL] + tst r0, #PMC_CTRL_SIDE_EFFECT_LP0 + beq lp1_clocks_prepare + + /* enable PLLM via PMC in LP0 */ + ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] + orr r0, r0, #((1<<12) | (1 << 11)) + str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] + mov pc, lr + /* start by jumping to clkm to safely disable PLLs, then jump * to clks */ +lp1_clocks_prepare: mov r0, #(1 << 28) str r0, [r5, #CLK_RESET_SCLK_BURST] str r0, [r5, #CLK_RESET_CCLK_BURST] @@ -539,20 +550,11 @@ tegra3_cpu_clk32k: #endif /* disable PLLM via PMC in LP1 */ - ldr r0, [r4, #PMC_CTRL] - tst r0, #PMC_CTRL_SIDE_EFFECT_LP0 - bne enable_pllm_lp0 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] bic r0, r0, #(1<<12) str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] b powerdown_pll_pcx -enable_pllm_lp0: - /* enable PLLM via PMC in LP0 */ - ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] - orr r0, r0, #((1<<12) | (1 << 11)) - str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] - powerdown_pll_pcx: /* disable PLLP, PLLA, PLLC, and PLLX in LP0 and LP1 states */ ldr r0, [r4, #PMC_CTRL] |