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author | Scott Williams <scwilliams@nvidia.com> | 2011-07-25 13:24:13 -0700 |
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committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:46:58 -0800 |
commit | b9e403190bbbe1225abd87185e7dfb4518a1e992 (patch) | |
tree | 69c8ad3a09d54f9545ea9325909db50042e54ff6 /arch/arm/mach-tegra/sleep-t3.S | |
parent | d177f4e51d81f29699f6041909c26ae43a27bd76 (diff) |
ARM: tegra: power: Add LP2 in idle support for secondary CPUs
Change-Id: Ie557f4429d65fb4cf701935b7ea6b1190140a878
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rf03d13e909ff708671ab09077d1de590182b9917
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
-rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 9a089a605378..abaea8b868f1 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -136,6 +136,22 @@ ENTRY(tegra3_sleep_cpu) ENDPROC(tegra3_sleep_cpu) /* + * tegra3_sleep_cpu_secondary(unsigned long v2p) + * + * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. + */ +ENTRY(tegra3_sleep_cpu_secondary) + mov r3, lr @ set resume address to lr + bl tegra_cpu_save + bl tegra_cpu_exit_coherency + + /* Powergate this CPU. */ + mov r0, #0 @ power mode flags (!hotplug) + bl tegra3_cpu_reset + b . @ should never get here +ENDPROC(tegra3_sleep_cpu_secondary) + +/* * tegra3_tear_down_cpu * * Switches the CPU cluster to PLL-P and enters sleep. |