diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-01-12 16:31:40 -0800 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2013-01-15 10:20:00 -0800 |
| commit | 13829a080601f7bec802233c35deee33a27bedf0 (patch) | |
| tree | 32b789550b1e03ab425e73950bbbd11fc3e1998f /arch/arm/mach-tegra/sleep-t3.S | |
| parent | 662996478361878c672a99338eaedf7b8e8d0f34 (diff) | |
ARM: tegra11: power: Don't enable PLLA in LP1 reset exit
Current code enables PLLA in LP1 reset exit simultaneously with PLLP
that supplies PLLA reference clock - it is not a valid h/w procedure.
Moreover, PLLA state is always restored later in common clock resume
procedure. This allows to completely remove PLLA restoration form the
LP1 reset exit.
Change-Id: I66e3b7575a5a1b975308880f3990a1f8175aaa18
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/190883
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index c157dd4f2df1..bc6a1bfea55e 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -337,7 +337,7 @@ tegra3_iram_start: ENTRY(tegra3_lp1_reset) /* the CPU and system bus are running at 32KHz and executing from * IRAM when this code is executed; immediately switch to CLKM and - * enable PLLP, PLLM, PLLC, PLLA and PLLX. */ + * enable PLLP, PLLM, PLLC, and PLLX. */ mov32 r0, TEGRA_CLK_RESET_BASE #ifndef CONFIG_TRUSTED_FOUNDATIONS /* secure code handles 32KHz to CLKM/OSC clock switch */ @@ -356,13 +356,11 @@ ENTRY(tegra3_lp1_reset) pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC - pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC pll_locked r1, r0, CLK_RESET_PLLM_BASE pll_locked r1, r0, CLK_RESET_PLLP_BASE - pll_locked r1, r0, CLK_RESET_PLLA_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE pll_locked r1, r0, CLK_RESET_PLLX_BASE |