ARM: tegra: power: Update PLL configuration in LP1 state

- Put Tegra11 PLLs (PLLM, PLLC, PLLX) in IDDQ mode during LP1 state
- Made sure Tegra30 style PLL lock detect control is not applied to
Tegra11 PLLs (it was overwriting some unrelated Tegra11 bits)
- Added Tegra30 PLL lock detect reset pulse (Bug 1198457)

Change-Id: Ib14a86ffdc24144620f1dc18cf8a0c4c23b6b3e2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191097
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

1 files changed, 55 insertions, 2 deletions

diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S
index bc6a1bfea55e..6bdd567dcac3 100644
--- a/arch/arm/mach-tegra/sleep-t3.S
+++ b/arch/arm/mach-tegra/sleep-t3.S
@@ -88,6 +88,12 @@
 #define CLK_RESET_PLLP_MISC		0xac
 #define CLK_RESET_PLLA_MISC		0xbc
 #define CLK_RESET_PLLX_MISC		0xe4
+#if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+#define CLK_RESET_PLLX_MISC3		0x518
+#define CLK_RESET_PLLM_MISC_IDDQ	5
+#define CLK_RESET_PLLC_MISC_IDDQ	26
+#define CLK_RESET_PLLX_MISC3_IDDQ	3
+#endif
 
 #define CLK_RESET_PLLP_OUTA		0xa4
 #define CLK_RESET_PLLP_OUTB		0xa8
@@ -319,9 +325,15 @@ tegra3_iram_start:
 	orreq	\rd, \rd, #(1<<30)
 	streq	\rd, [\car, #\base]
 #if USE_PLL_LOCK_BITS
+	.if	\misc
+	ldr	\rd, [\car, #\misc]
+	bic	\rd, \rd, #(1<<18)
+	str	\rd, [\car, #\misc]
+	ldr	\rd, [\car, #\misc]
 	ldr	\rd, [\car, #\misc]
 	orr	\rd, \rd, #(1<<18)
 	str	\rd, [\car, #\misc]
+	.endif
 #endif
 .endm
 
@@ -334,6 +346,18 @@ tegra3_iram_start:
 #endif
 .endm
 
+.macro pll_iddq_exit, rd, car, iddq, iddq_bit
+	ldr	\rd, [\car, #\iddq]
+	bic	\rd, \rd, #(1<<\iddq_bit)
+	str	\rd, [\car, #\iddq]
+.endm
+
+.macro pll_iddq_entry, rd, car, iddq, iddq_bit
+	ldr	\rd, [\car, #\iddq]
+	orr	\rd, \rd, #(1<<\iddq_bit)
+	str	\rd, [\car, #\iddq]
+.endm
+
 ENTRY(tegra3_lp1_reset)
 	/* the CPU and system bus are running at 32KHz and executing from
 	 * IRAM when this code is executed; immediately switch to CLKM and
@@ -348,6 +372,8 @@ ENTRY(tegra3_lp1_reset)
 	str	r1, [r0, #CLK_RESET_SCLK_DIVIDER]
 	str	r1, [r0, #CLK_RESET_CCLK_DIVIDER]
 #endif
+
+#if defined(CONFIG_ARCH_TEGRA_3x_SOC)
 	/* enable PLLM via PMC */
 	mov32	r2, TEGRA_PMC_BASE
 	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
@@ -355,9 +381,29 @@ ENTRY(tegra3_lp1_reset)
 	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
 
 	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
-	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
 	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
 	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
+#else
+	pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
+	pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
+	pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
+
+	mov32	r7, TEGRA_TMRUS_BASE
+	ldr	r1, [r7]
+	add	r1, r1, #2
+	wait_until r1, r7, r3
+
+	/* enable PLLM via PMC */
+	mov32	r2, TEGRA_PMC_BASE
+	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
+	orr	r1, r1, #(1<<12)
+	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
+
+	pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
+	pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
+	pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
+#endif
+	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
 
 	pll_locked r1, r0, CLK_RESET_PLLM_BASE
 	pll_locked r1, r0, CLK_RESET_PLLP_BASE
@@ -755,7 +801,14 @@ powerdown_pll_cx:
 	ldr	r0, [r5, #CLK_RESET_PLLX_BASE]
 	bic	r0, r0, #(1<<30)
 	str	r0, [r5, #CLK_RESET_PLLX_BASE]
-
+#if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+	/*
+	 * FIXME: put PLLM into IDDQ (need additional testing)
+	 * pll_iddq_entry r1, r5, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
+	 */
+	pll_iddq_entry r1, r5, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
+	pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
+#endif
 	mov	pc, lr
 
 /*