diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-01-14 21:20:56 -0800 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2013-01-17 17:07:00 -0800 |
| commit | 31615e1677a5e76ca90622cf2756aa09c0e17286 (patch) | |
| tree | 3636f303ee30d87ab8bc8b1be7db4d3404ce86f5 /arch/arm/mach-tegra/sleep-t3.S | |
| parent | 2b8d8704295e1aba2328559fa978750505535e49 (diff) | |
ARM: tegra: power: Defer switch to 32kHz on LP1 entry
Deferred switching system clock to 32kHz source after all PLLs are
disabled. There is no need to slow down entry procedure by PLLs
manipulation in 32kHz domain.
Change-Id: I2cfad09f80baa9deda8626ae78cbfcc3326dc7d3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/191111
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 6bdd567dcac3..6f10cfba7e20 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -772,10 +772,6 @@ lp1_volt_skip: add r1, r1, #2 wait_until r1, r7, r9 - /* switch to CLKS */ - mov r0, #0 /* burst policy = 32KHz */ - str r0, [r5, #CLK_RESET_SCLK_BURST] - /* disable PLLM via PMC in LP1 */ ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] bic r0, r0, #(1 << 12) @@ -809,6 +805,10 @@ powerdown_pll_cx: pll_iddq_entry r1, r5, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ #endif + + /* switch to CLKS */ + mov r0, #0 /* burst policy = 32KHz */ + str r0, [r5, #CLK_RESET_SCLK_BURST] mov pc, lr /* |