diff options
author | Alex Frid <afrid@nvidia.com> | 2012-06-23 23:50:54 -0700 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-07-16 18:25:54 +0530 |
commit | 6bcc352e1b0bd6d032a8597ee836b7bac3e14066 (patch) | |
tree | 2a24fbdd1e9bf37528e4e69100accc4297c18846 /arch/arm/mach-tegra/sleep-t3.S | |
parent | e3477cfe9f942634889a68b4123167a5485c3bbd (diff) |
ARM: tegra: clock: Allow Tegra3 PLLM rate change
Allowed Tegra3 memory PLLM rate change, provided it is disabled.
Since PLLM can deviate from boot configuration now, and on Tegra3 it
is controlled by PMC override registers (not CAR module registers):
- Re-factored PLLM initialization, resume, and set rate operations
accordingly (enable and disable ops already used PMC override).
- Made sure that boot configuration is restored on entry to LP0 to
match memory timing saved in scratch registers.
Bug 1005576
Change-Id: Iac6297455bec709a8e12d71deccab62c18905ea7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/110937
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit b53f88c68543a2b0ddb4545bb3b389b42eeb95d8)
Reviewed-on: http://git-master/r/114759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
-rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 9433eb6886b3..a55ad44e2f57 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -91,6 +91,7 @@ #define CLK_RESET_PLLP_OUTB 0xa8 #define PMC_PLLP_WB0_OVERRIDE 0xf8 +#define PMC_PLLM_WB0_OVERRIDE 0x1dc #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 @@ -552,10 +553,12 @@ tegra3_cpu_clk32k: tst r0, #PMC_CTRL_SIDE_EFFECT_LP0 beq lp1_clocks_prepare - /* enable PLLM via PMC in LP0 */ + /* enable PLLM auto-restart via PMC in LP0; restore override settings */ ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] orr r0, r0, #((1 << 12) | (1 << 11)) str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] + ldr r0, [r4, #PMC_SCRATCH2] + str r0, [r4, #PMC_PLLM_WB0_OVERRIDE] mov pc, lr /* start by jumping to clkm to safely disable PLLs, then jump |