diff options
| author | Bo Yan <byan@nvidia.com> | 2012-05-18 19:38:05 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-06-28 18:17:38 +0530 |
| commit | 7d14fd7de454722ed6c34ccf2bad00828b5af4c4 (patch) | |
| tree | 4f9fa50094ed022d6f4e87d07cd732c11fc0c326 /arch/arm/mach-tegra/sleep-t3.S | |
| parent | fa4883c14e87b3cc4080b3ec9dc9be4264dc8051 (diff) | |
ARM: tegra11: Update cache flush/invalidate for power gating
The field ENABLE_EXT in CSR register controls what power partition
to be gated. If it's CPU-partition power gating only, there is no
need to flush or invalidate L2 cache before/after power gating.
With this change, L2 cache is flushed/invalidated only when the
non-CPU partition is to be power gated or when rail gating is
selected.
Change-Id: I6be522de694117a058eedc9584f2157d89f99dc4
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/103476
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index af0da7452575..472266a261d9 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -245,10 +245,25 @@ ENTRY(tegra3_sleep_cpu_secondary_finish) dsb #ifdef MULTI_CACHE +#ifdef CONFIG_HAVE_ARM_SCU mov32 r10, cpu_cache mov lr, pc ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] #else + cpu_id r2 + cpu_to_csr_reg r1, r2 + mov32 r10, TEGRA_FLOW_CTRL_VIRT + ldr r10, [r10, r1] + tst r10, #FLOW_CTRL_CSR_ENABLE_EXT_MASK + beq flush_l1 + mov32 r10, cpu_cache + mov lr, pc + ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] + b no_l2_sync +flush_l1: + bl tegra_flush_l1_cache +#endif +#else bl __cpuc_flush_kern_all #endif |