diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2012-09-14 12:45:53 +0300 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-09-18 05:55:07 -0700 |
| commit | 99922defb05b03b1331c4a7778cb0dde0320f3a4 (patch) | |
| tree | a687f05588efa92a293efa0ba2929f57cf7cf45f /arch/arm/mach-tegra/sleep-t3.S | |
| parent | 071b55b3762b4770636f834b2f0d0ed7d4a0967d (diff) | |
ARM: Tegra: Disable data cache before flush
When entering power gating, disable L1 data cache before
flushing. This is needed in order to prevent data cache
making allocations during/after flushing.
Bug 1045096
Change-Id: I0a6b2516e2bbd21ca35b74d24f7311318e127607
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/132590
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 5c7782f64407..fdc7b9ad3a09 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -264,12 +264,7 @@ ENTRY(tegra3_sleep_cpu_secondary_finish) mov r6, lr dsb -#ifdef MULTI_CACHE -#ifdef CONFIG_HAVE_ARM_SCU - mov32 r10, cpu_cache - mov lr, pc - ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] -#else + /* Disable the data cache */ mrc p15, 0, r2, c1, c0, 0 bic r2, r2, #CR_C @@ -277,6 +272,13 @@ ENTRY(tegra3_sleep_cpu_secondary_finish) mcr p15, 0, r2, c1, c0, 0 isb +#ifdef MULTI_CACHE +#ifdef CONFIG_HAVE_ARM_SCU + mov32 r10, cpu_cache + mov lr, pc + ldr pc, [r10, #CACHE_FLUSH_KERN_ALL] +#else + cpu_id r2 cpu_to_csr_reg r1, r2 mov32 r10, TEGRA_FLOW_CTRL_VIRT |