diff options
| author | Nikesh Oswal <noswal@nvidia.com> | 2011-12-20 15:56:24 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:49:51 -0700 |
| commit | b5d68fe07a0618f4aec548defd3c6cb01be85fd8 (patch) | |
| tree | 0ab21d0ba0770279bad5f2235c462b45075dec78 /arch/arm/mach-tegra/sleep-t3.S | |
| parent | 77cc06d1f6def1f8ae5f543a6163d4a844bb5114 (diff) | |
arm: tegra: pm: do not turn off PLL-P & PLL-A for LP1 on Tegra3
Bug: 917672
Change-Id: Ie3446f7fdaa05a6dab43375b842b37070cea33b7
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/71173
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Rebase-Id: R8628592b81a75836e12711af32e57bb571d6a856
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 4938114c88ad..0d7a16bd7c5e 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -554,12 +554,16 @@ enable_pllm_lp0: powerdown_pll_pcx: /* disable PLLP, PLLA, PLLC, and PLLX in LP0 and LP1 states */ + ldr r0, [r4, #PMC_CTRL] + tst r0, #PMC_CTRL_SIDE_EFFECT_LP0 + beq powerdown_pll_cx ldr r0, [r5, #CLK_RESET_PLLP_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLP_BASE] ldr r0, [r5, #CLK_RESET_PLLA_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLA_BASE] +powerdown_pll_cx: ldr r0, [r5, #CLK_RESET_PLLC_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLC_BASE] |