diff options
| author | Ajay Nandakumar <anandakumarm@nvidia.com> | 2013-09-17 16:53:00 +0530 |
|---|---|---|
| committer | Bharat Nihalani <bnihalani@nvidia.com> | 2013-09-20 01:43:22 -0700 |
| commit | 24bf858adc9f92212175bf44a9cd77d3f90106fe (patch) | |
| tree | 4b7df7b3d650748c4a004ec1f0f2127561ff390e /arch/arm/mach-tegra/sleep-t30.S | |
| parent | a9b421b4a046bd3008e4c7b939dafe3306fa2684 (diff) | |
Revert "arm: tegra: save and restore EMC_REFRESH value"
This reverts commit 5fd27c0a74265731edb771ed91680a658dc9f7bf.
Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com>
Conflicts:
arch/arm/mach-tegra/sleep-t30.S
Change-Id: I8bca16191a03924d02658f33f0158dbf84f06e6a
Reviewed-on: http://git-master/r/275718
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 41 |
1 files changed, 17 insertions, 24 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index a653092fa97b..73b2b811cf88 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -480,10 +480,10 @@ defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) add r5, pc, #tegra11_sdram_pad_save-(.+8) @ r5 --> saved data #endif - ldr r4, [r5, #0x1c] + ldr r4, [r5, #0x18] str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] - ldr r4, [r5, #0x20] + ldr r4, [r5, #0x1C] str r4, [r0, #CLK_RESET_SCLK_BURST] #if defined(CONFIG_ARCH_TEGRA_3x_SOC) mov32 r4, ((1<<28) | (8)) @ burst policy is PLLX @@ -602,7 +602,7 @@ defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) add r5, pc, #tegra11_sdram_pad_save-(.+8) @ r5 --> saved data #endif - ldr r1, [r5, #0x18] @ PMC_IO_DPD_STATUS + ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS mvn r1, r1 bic r1, r1, #(0x1<<31) orr r1, r1, #(0x1<<30) @@ -649,7 +649,6 @@ emc_wait_audo_cal_onetime: str r1, [r0, #EMC_NOP] str r1, [r0, #EMC_NOP] #endif - ldr r1, [r5, #0x14] #if defined(CONFIG_ARCH_TEGRA_3x_SOC) str r1, [r0, #EMC_REFRESH] #endif @@ -722,7 +721,7 @@ zcal_done: mov32 r1, TEGRA_EMC1_BASE cmp r0, r1 movne r0, r1 - addne r5, r5, #0x24 + addne r5, r5, #0x20 bne exit_self_refresh #endif @@ -754,7 +753,6 @@ tegra3_sdram_pad_save: .word 0 .word 0 .word 0 - .word 0 tegra3_sdram_pad_address: .word TEGRA_EMC_BASE + EMC_CFG @0x0 @@ -762,11 +760,10 @@ tegra3_sdram_pad_address: .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 - .word TEGRA_EMC_BASE + EMC_REFRESH @0x14 - .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x18 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x1c - .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x20 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_CCLK_BURST @0x24 + .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CCLK_BURST @0x20 #endif #if defined(CONFIG_ARCH_TEGRA_11x_SOC) .align L1_CACHE_SHIFT @@ -786,8 +783,6 @@ tegra11_sdram_pad_save: .word 0 .word 0 .word 0 - .word 0 - .word 0 tegra11_sdram_pad_address: .word TEGRA_EMC0_BASE + EMC_CFG @0x0 @@ -795,17 +790,15 @@ tegra11_sdram_pad_address: .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10 - .word TEGRA_EMC0_BASE + EMC_REFRESH @0x14 - .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x18 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x1c - .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x20 - .word TEGRA_CLK_RESET_BASE + CLK_RESET_CCLK_BURST @0x24 - .word TEGRA_EMC1_BASE + EMC_CFG @0x28 - .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x2c - .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x30 - .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x34 - .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x38 - .word TEGRA_EMC1_BASE + EMC_REFRESH @0x3c + .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 + .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c + .word TEGRA_CLK_RESET_BASE + CLK_RESET_CCLK_BURST @0x20 + .word TEGRA_EMC1_BASE + EMC_CFG @0x24 + .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x28 + .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x2c + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x30 + .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x34 #endif #ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE |