ARM: tegra14x: Enable LP1BB->LP1 transition

If an LP1BB wake was caused solely due to the
end of paging event (i.e mem_req->0), we should
transition to LP1 without waking to active.

Bug 1239689

Change-Id: Ib3f8c1a74386f87a4e7d5f10878ef919bb5be6e1
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/204901
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>

1 files changed, 54 insertions, 1 deletions

diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
index e4c7c45b862e..47874ba86156 100644
--- a/arch/arm/mach-tegra/sleep-t30.S
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -511,12 +511,65 @@ powerup_l2_done:
 #endif
 
 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
+
+	/* If we are waking up from LP1, unconditionally continue
+	 * resume.
+	 */
 	mov32	r4, TEGRA_PMC_BASE
 	ldr	r0, [r4, #PMC_LP_STATE_SCRATCH_REG]
 	mov	r0, r0, lsr #PMC_LP_STATE_BIT_OFFSET
 	and	r0, r0, #PMC_LP_STATE_BIT_MASK
-	cmp	r0, #PMC_LP_STATE_LP1BB
+	cmp	r0, #PMC_LP_STATE_LP1
+	beq	lp1_exit_resume
+
+	/* If we are waking up from LP1BB, see the wake source.
+	 * If it was mem_req=0, then go into LP1.
+	 * Otherwise wake to active.
+	 */
+	ldr	r0, [r4, #PMC_WAKE2_STATUS]
+	tst	r0, #PMC_WAKE2_BB_MEM_REQ
+
+	/* If it isn't mem_req=0, continue with resume, just
+	 * skip self refresh routine
+	 */
 	beq	self_refresh_skip
+
+	/* If it is mem_req=0, check to see if there was another
+	 * wake event, if yes, continue with wake to active
+	 */
+	ldr	r1, [r4, #PMC_WAKE_STATUS]
+
+	/* Mask out other wake events from WAKE2_STATUS */
+	bic	r0, r0, #PMC_WAKE2_BB_MEM_REQ
+	orrs	r1, r1, r0
+
+	/* If there were any other wake events, wake to active */
+	bne	self_refresh_skip
+
+	/* Since the wake was mem_req, we need to enter LP1 */
+	mov32	r5, TEGRA_CLK_RESET_BASE
+	mov32	r6, TEGRA_FLOW_CTRL_BASE
+	mov32	r7, TEGRA_TMRUS_BASE
+
+	/* Write PMC_IPC_CLR[mem_sts] = 1 */
+	ldr     r1, [r4, #PMC_IPC_CLR]
+	orr     r1, r1, #PMC_IPC_CLR_MEM_STS
+	str     r1, [r4, #PMC_IPC_CLR]
+
+	/* Set lp state variable */
+	mov	r0, #PMC_LP_STATE_LP1
+	str	r0, lp_enter_state
+	bl	tegra148_set_lp_state
+
+	/* Set mem_req=1 interrupt */
+	bl	tegra148_set_mem_req_interrupt
+
+	/* Legacy LP1 entry routine */
+	bl	tegra3_sdram_self_refresh
+	bl	tegra3_cpu_clk32k
+	b	tegra3_enter_sleep
+
+lp1_exit_resume:
 #endif
 
 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)