diff options
| author | Karthik Ramakrishnan <karthikr@nvidia.com> | 2013-01-25 15:05:33 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:06:48 -0700 |
| commit | b12099cf487848b4e035d0070aa4317ffd988077 (patch) | |
| tree | c9c4a93311fd08baceef0599431c4dd79cf476ec /arch/arm/mach-tegra/sleep-t30.S | |
| parent | ca6f9bb152ee589b20e670d724cdf0c7e59d1956 (diff) | |
arm: tegra: LP1 Low Core Voltage Support for T114
The feature was added for T30 and the config name referred to
the lowest Core voltage for Enterprise(CONFIG_TEGRA_LP1_950).
Changed the Kconfig to include T114 support and renamed the
feature name to refer to the lowest Core voltage possible for
the particular platform and not just 950mV.
The initial change for this feature is in http://git-master/r/124135
Bug 1035684
Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Signed-off-by: Hunk Lin <hulin@nvidia.com>
(cherry picked from commit c94f740ede4809a897e18253a9c7fdfb8666970e)
Reviewed-on: http://git-master/r/194260
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 904cd34bb286..7b188ab0604f 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -467,7 +467,7 @@ ENTRY(tegra3_lp1_reset) str r4, [r0, #CLK_RESET_CCLK_BURST] #endif -#ifdef CONFIG_TEGRA_LP1_950 +#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE lp1_voltset: /* Restore the Core voltage to high on LP1 resume */ /* Reset(Enable/Disable) the DVC-I2C Controller*/ @@ -802,7 +802,7 @@ tegra11_sdram_pad_address: .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 #endif -#ifdef CONFIG_TEGRA_LP1_950 +#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE .globl lp1_register_pmuslave_addr .globl lp1_register_i2c_base_addr .globl lp1_register_core_lowvolt @@ -1002,7 +1002,7 @@ tegra3_cpu_clk32k: lp1_clocks_prepare: /* Prepare to set the Core to the lowest voltage if supported. * Start by setting the I2C clocks to make the I2C transfer */ -#ifdef CONFIG_TEGRA_LP1_950 +#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE /* Set up the PWR I2C GPIOs with the right masks*/ /* Reset(Set/Clr) the DVC-I2C Controller*/ |