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| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-11-14 17:55:55 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:50:16 -0800 |
| commit | 1b4bcbe04e979846377b23bc3d879ed5ffc43e6d (patch) | |
| tree | b4b23060d3d1405f5539b1b2c777b86570e605ce /arch/arm/mach-tegra/sleep.S | |
| parent | b06fa5c20b40847da6c8fc1f122f56820222b6aa (diff) | |
ARM: tegra: power: L2 cache sync only for CPU0 LP2
Bug 901430
Bug 905813
Change-Id: Id57f870262eebe6a2017b808d1a66624f903989d
Reviewed-on: http://git-master/r/64103
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc3cad5fafa9e62fa10099bc4dc1281954a04b8f5
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 1f57f6fef617..e041f2d5368e 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -246,6 +246,11 @@ ENTRY(tegra_cpu_suspend) bl __cpuc_flush_kern_all #endif #ifdef CONFIG_CACHE_L2X0 +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + cpu_id r2 + cmp r2, #0 + bne no_l2_sync +#endif /* Issue a PL310 cache sync operation */ dsb mov32 r2, TEGRA_PL310_VIRT @@ -255,6 +260,7 @@ ENTRY(tegra_cpu_suspend) str r1, [r2] #endif +no_l2_sync: /* Invalidate the TLBs & BTAC */ mov r1, #0 mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs |