diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-06-29 10:40:33 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:49 -0800 |
| commit | aedd82b51df78e5beef6cf34478e5b500be71ecf (patch) | |
| tree | c5d18d4d1b0d60ba9d47c142310dac9ae45927ec /arch/arm/mach-tegra/sleep.S | |
| parent | f944d3f344ca055c0bbba80010ca2b6786c27bb3 (diff) | |
ARM: tegra: power: remove unnecessary barriers on LP3 idle loop
Removed unnecessary barriers by removing the read-back of the flow
controller halt register. The delay caused by the readback gets
worse as the number of cores increase. By using raw writes instead,
page fault handler performance improves siginificantly.
In addition, the flow controller CSR interrupt and event status is
cleared to ensure proper operation on Tegra3.
Change-Id: I92d0a1487a16c39438038b9bfff591bc69195ab8
Reviewed-on: http://git-master/r/40461
Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R98ecb17b3cdec99f69f7067ec7bdd7b00d789da9
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 26 |
1 files changed, 15 insertions, 11 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 5075a9c2379f..11e38f2aaa34 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, NVIDIA Corporation. + * Copyright (c) 2010-2011, NVIDIA Corporation. * Copyright (c) 2011, Google, Inc. * * Author: Colin Cross <ccross@android.com> @@ -69,6 +69,9 @@ #define FLOW_CTRL_IRQ_RESUME (1 << 10) #define FLOW_CTRL_FIQ_RESUME (1 << 8) +#define FLOW_CTRL_CSR_INTR_FLAG (1<<15) +#define FLOW_CTRL_CSR_EVENT_FLAG (1<<14) + #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT) #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) @@ -193,25 +196,26 @@ ENDPROC(tegra_cpu_save) * tegra_cpu_wfi * * puts current CPU in clock-gated wfi using the flow controller - * if the state is saved before calling tegra_cpu_wfi, the cpu can go from - * wfi directly to reset * - * corrupts r0-r2 + * corrupts r0-r3 * must be called with MMU on */ ENTRY(tegra_cpu_wfi) cpu_id r0 cpu_to_halt_reg r1, r0 + cpu_to_csr_reg r2, r0 mov32 r0, TEGRA_FLOW_CTRL_VIRT - mov r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME - str r2, [r0, r1] @ put flow controller in wait event mode - ldr r2, [r0, r1] - isb + mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + str r3, [r0, r2] @ clear event & interrupt status + mov r3, #FLOW_CTRL_STOP_UNTIL_IRQ | FLOW_CTRL_JTAG_RESUME + str r3, [r0, r1] @ put flow controller in wait irq mode dsb wfi - mov r2, #0 - str r2, [r0, r1] - ldr r2, [r0, r1] + mov r3, #0 + str r3, [r0, r1] @ clear flow controller halt status + mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + str r3, [r0, r2] @ clear event & interrupt status + dsb mov pc, lr ENDPROC(tegra_cpu_wfi) |