diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-08-12 10:21:35 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:04 -0800 |
| commit | bb4569a5ca7dc1a44e33b689e36fe1b320774d87 (patch) | |
| tree | 126b7b2bdedce3d7e54c5cffc7e0328e979a898f /arch/arm/mach-tegra/sleep.S | |
| parent | 8c2d2cd9c82333bdf813c28675353e3c93a0b7d2 (diff) | |
ARM: tegra: power: Perform L2 cache sync when flushing L1
Change-Id: I7b769bec8fc2dc0cd6db34e125f1cfd45aea8b12
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rcf33e9438333a90b3aa9bf29925a277d65317f84
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 64ba9c2eadfd..5d8a804665a2 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -48,6 +48,7 @@ #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) +#define TEGRA_PL310_VIRT (TEGRA_ARM_PL310_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) /* * tegra_pen_lock @@ -244,6 +245,15 @@ ENTRY(tegra_cpu_suspend) #else bl __cpuc_flush_kern_all #endif +#ifdef CONFIG_CACHE_L2X0 + /* Issue a PL310 cache sync operation */ + dsb + mov32 r2, TEGRA_PL310_VIRT + movw r1, 0x730 @ cache sync + add r2, r2, r1 + mov r1, #0 + str r1, [r2] +#endif /* Invalidate the TLBs & BTAC */ mov r1, #0 |