diff options
| author | Sang-Hun Lee <sanlee@nvidia.com> | 2012-04-16 10:53:37 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-04-19 07:40:13 -0700 |
| commit | fce62841d65737d001b083db0a74525a9d611dfc (patch) | |
| tree | eb9f8985164677f879945ac168dc5d0e4e14e423 /arch/arm/mach-tegra/sleep.S | |
| parent | 4fa4ef0ac97433028ad84f9df1266790c44651e7 (diff) | |
Restore "ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmu"
This restores commit 607d5ec8bb46f95473533f611da1ffc97907d16e.
The common ARM CPU state suspend/resume code does not work with
and external L2 cache controller (like a PL310) enabled. This
change fixes corruption of the current PMD by the MMU resume code.
cpu_resume_mmu modifies the currently active page tables to add
a flat (VA==PA) section mapping of cpu_resume_turn_mmu_on to
handle MMU off-to-on transition. It turns off the L1 data cache
but it knows nothing of the L2 cache. Since page table walks are
L2 cacheable, other CPUs in the system can pick up the corrupted
PMD which will eventually result in a kernel panic.
The workaround for this is to modify push_ctx_regs to save the
current TTB0 and CONTEXID registers in the CPU register context
and switch to the private tegra_pgd before saving the rest of the
CPU context. The tegra_pgd already has a flat mapping for the
code in question, so it can't be damaged by the actions of
cpu_resume_mmu. Likewise, pop_ctx_regs is modified to restore
the actual TTB0 and CONTEXTID registers when restoring the CPU
registers.
Bug 967887
Change-Id: Iaf98c46359860531874354e8cddabe299ea90d57
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/96789
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 003de98acd03..973c8677bafe 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -395,27 +395,6 @@ tegra_cpu_resume: * r1 = physical address to jump to with mmu off */ ENTRY(tegra_turn_off_mmu) - /* - * change page table pointer to tegra_pgd_phys, so that IRAM - * and MMU shut-off will be mapped virtual == physical - */ - mrc p15, 0, r2, c2, c0, 0 @ TTB 0 - mov32 r3, ~PAGE_MASK - and r2, r2, r3 - ldr r3, tegra_pgd_phys_address - ldr r3, [r3] - orr r3, r3, r2 - mov r2, #0 - mcr p15, 0, r2, c13, c0, 1 @ reserved context - isb - mcr p15, 0, r3, c2, c0, 0 @ TTB 0 - isb - - mov r2, #0 - mcr p15, 0, r2, c8, c3, 0 @ invalidate TLB - mcr p15, 0, r2, c7, c5, 6 @ flush BTAC - mcr p15, 0, r2, c7, c5, 0 @ flush instruction cache - mov32 r3, tegra_shut_off_mmu add r3, r3, r0 mov r0, r1 |