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authorScott Williams <scwilliams@nvidia.com>2011-08-03 17:33:37 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:47:01 -0800
commit68437fa5d8cf810c58643b364f906cb7ae29561f (patch)
treeeb7c4196a9858acd34913a2e9f45d851e422518a /arch/arm/mach-tegra/sleep.S
parenta0f57a8931b76c3f63299b3715b3629a613c1bf9 (diff)
ARM: tegra: power: Add SMP coherency exit macro
Define the SMP coherency exit code as a macro to allow it to be inlined in assembly code that needs to control its register usage. Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
-rw-r--r--arch/arm/mach-tegra/sleep.S12
1 files changed, 1 insertions, 11 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 36dff782f3fa..9b436c9512a2 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -47,7 +47,6 @@
#define CLK_RESET_CCLK_DIVIDER 0x24
#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
-#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT)
#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT)
/*
@@ -139,16 +138,7 @@ ENDPROC(tegra_cpu_wfi)
* corrupts r4-r5
*/
ENTRY(tegra_cpu_exit_coherency)
- mrc p15, 0, r4, c1, c0, 1 @ ACTLR
- bic r4, r4, #(1<<6) @ exit coherency: clear ACTLR.SMP
- mcr p15, 0, r4, c1, c0, 1 @ ACTLR
- isb
- cpu_id r4
- mov r4, r4, lsl #2
- mov r5, #0xf
- mov r5, r5, lsl r4
- mov32 r4, TEGRA_ARM_PERIF_VIRT + 0xC
- str r5, [r4] @ invalidate SCU tags for CPU
+ exit_smp r4, r5
mov pc, lr
ENDPROC(tegra_cpu_exit_coherency)