diff options
| author | Bo Yan <byan@nvidia.com> | 2012-09-19 18:19:37 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-10-10 22:20:15 -0700 |
| commit | 23e9717734862ebbe9ddb03253a47749fb1e84ef (patch) | |
| tree | 3d5d26c6e795d9b6288ea34ffe466a9975eba3a2 /arch/arm/mach-tegra/sleep.S | |
| parent | 4eb3d0d8fd5ba190131aba64804a808d76078dfa (diff) | |
ARM: tegra: cluster switch for T11x
1. for secondary CPU, always flush L1 only, this is irrespective of
Cortex A9 or Cortex A15
2. disable cache before flushing it when rail-gating CPU0
3. do not flush cache before entering ARM common code cpu_suspend,
which by itself will flush cache.
Still, it's highly desirable to flush cache in __cpu_suspend_save,
since this will flush L2 irrespective of A9 or A15.
Reviewed-on: http://git-master/r/133945
Change-Id: I2c6eb20546b5fc8b5432dc73c2f97480cbf29ee8
Signed-off-by: Bo Yan <byan@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/143126
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 79ee18cd09b6..4cc02ed7b102 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -223,6 +223,9 @@ ENDPROC(tegra_flush_l1_cache) * tegra?_tear_down_cpu */ ENTRY(tegra_sleep_cpu_finish) + mov r4, r0 + bl tegra_flush_cache + mov r0, r4 bl tegra_cpu_exit_coherency #ifdef CONFIG_ARCH_TEGRA_2x_SOC |