diff options
| author | Colin Cross <ccross@android.com> | 2011-08-23 17:43:54 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-21 22:14:21 -0700 |
| commit | 614a942d332591073de19d6d6098453c3003aee8 (patch) | |
| tree | a5054166fc55105138d21af17b6265fb83ef4f97 /arch/arm/mach-tegra/sleep.S | |
| parent | fcda74d8e8ce96cbbda78b430ad2cac77887799b (diff) | |
ARM: tegra: sleep: flush tlbs when exiting wfi
tegra_sleep_wfi disables coherency to prepare for possibly
resetting the cpu. If an interrupt is received, it exits
wfi and re-enables coherency, but it was not flushing the
tlbs or the branch predictor array, which could have been
updated by broadcast tlb operations that were ignored.
Flush the tlbs and branch predictor array when exiting.
Change-Id: If2c6ca3f923baf2f883f461a2a90f08833c7e191
Signed-off-by: Colin Cross <ccross@android.com>
Rebase-Id: Re46c9045a33ad78789e7dee2788b470fd1071c83
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 0c74e4ecd774..80aaca31fe52 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -316,6 +316,9 @@ ENTRY(tegra_sleep_wfi) mcr p15, 0, r11, c1, c0, 1 @ reenable coherency @ the cpu was running with coherency disabled, caches may be out of date + mov r0, #0 + mcr p15, 0, r0, c8, c3, 0 @ invalidate TLB + mcr p15, 0, r0, c7, c5, 6 @ flush BTAC #ifdef MULTI_CACHE ldr r10, =cpu_cache mov lr, pc |