diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-06-23 23:50:54 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-07-13 05:48:41 -0700 |
| commit | c9ce3ff77d029d99ddae5577b8358258feff08a0 (patch) | |
| tree | 536d68b03b7961e53813b4b93147f8562df3fd53 /arch/arm/mach-tegra/sleep.h | |
| parent | 3eeffbc3d34d05b668234306a7de2e157db9b8db (diff) | |
ARM: tegra: clock: Allow Tegra3 PLLM rate change
Allowed Tegra3 memory PLLM rate change, provided it is disabled.
Since PLLM can deviate from boot configuration now, and on Tegra3 it
is controlled by PMC override registers (not CAR module registers):
- Re-factored PLLM initialization, resume, and set rate operations
accordingly (enable and disable ops already used PMC override).
- Made sure that boot configuration is restored on entry to LP0 to
match memory timing saved in scratch registers.
Bug 1005576
Change-Id: Iac6297455bec709a8e12d71deccab62c18905ea7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/110937
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit b53f88c68543a2b0ddb4545bb3b389b42eeb95d8)
Reviewed-on: http://git-master/r/114759
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.h')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 7d086e00a835..c57399985ecd 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -50,6 +50,8 @@ #define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) +/* PMC_SCRATCH2 is used for PLLM boot state if PLLM auto-restart is enabled */ +#define PMC_SCRATCH2 0x58 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock in Tegra2 idle */ #define PMC_SCRATCH37 0x130 #define PMC_SCRATCH38 0x134 |