diff options
author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-04-24 14:26:28 +0530 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:09:50 -0700 |
commit | caf4dc49761caf71b762a9b894e23871c601bcf2 (patch) | |
tree | a61ddaef12fa4284f5b5f748ce7320e41c1f9257 /arch/arm/mach-tegra/tegra11_soctherm.h | |
parent | 151ff3a7c6c84fca0e7f45e4dab13f8cb2011367 (diff) |
ARM: tegra: soctherm: add OC interrupt support
The soctherm_oc pins are generally connected to the device
OC pins and sometimes this pins from device act as interrupt
line also.
In this case, it is require to act the tegra oc pin as SFIO and
route the interrupt call to device's isr.
Adding OC interrupt support so that soctherm can provide the interrupt
number and device can register with this irq number for handling their
interrupts.
Change-Id: I9e5eb75f0b919d2c6654acaa63242057d6c14438
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/215055
(cherry picked from commit cb76cf5609787c416e9516e5b9cb72d63efd28eb)
Reviewed-on: http://git-master/r/222397
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'arch/arm/mach-tegra/tegra11_soctherm.h')
-rw-r--r-- | arch/arm/mach-tegra/tegra11_soctherm.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra11_soctherm.h b/arch/arm/mach-tegra/tegra11_soctherm.h index a676809692cd..15484250a73d 100644 --- a/arch/arm/mach-tegra/tegra11_soctherm.h +++ b/arch/arm/mach-tegra/tegra11_soctherm.h @@ -58,6 +58,15 @@ enum soctherm_throttle_dev_id { THROTTLE_DEV_SIZE, }; +enum soctherem_oc_irq_id { + TEGRA_SOC_OC_IRQ_1, + TEGRA_SOC_OC_IRQ_2, + TEGRA_SOC_OC_IRQ_3, + TEGRA_SOC_OC_IRQ_4, + TEGRA_SOC_OC_IRQ_5, + TEGRA_SOC_OC_IRQ_MAX, +}; + struct soctherm_sensor { bool sensor_enable; bool zone_enable; @@ -116,6 +125,8 @@ struct soctherm_tsensor_pmu_data { }; struct soctherm_platform_data { + int oc_irq_base; + int num_oc_irqs; unsigned long soctherm_clk_rate; unsigned long tsensor_clk_rate; |