diff options
| author | Suresh Mangipudi <smangipudi@nvidia.com> | 2012-12-17 16:19:11 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2012-12-19 13:41:42 -0800 |
| commit | 4de2cc7c70ab9cd4f2790901b0535ffbd67f80da (patch) | |
| tree | e7e5597b2159e3672b1a4f9d4e58c8fe67940c0e /arch/arm/mach-tegra/tegra11x_usb_phy.c | |
| parent | 40d0427d400e522a0c0bc16cd73801e1b08fcbe4 (diff) | |
ARM: tegra: usb_phy: Fix T11x OverCurrent selection bit
The OCA bit in PORTSC is being set by default, this results in PORTSC
register reporting false status for over current.
Update the programming sequence such that the over_current bit is
cleared.
Bug 1199299
Change-Id: I17b2e6c48719986a87683da9ff52ff8874d7671d
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/171886
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra11x_usb_phy.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra11x_usb_phy.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra11x_usb_phy.c b/arch/arm/mach-tegra/tegra11x_usb_phy.c index a3627122a568..d1b33b7c7618 100644 --- a/arch/arm/mach-tegra/tegra11x_usb_phy.c +++ b/arch/arm/mach-tegra/tegra11x_usb_phy.c @@ -478,6 +478,16 @@ #define APB_MISC_GP_OBSCTRL_0 0x818 #define APB_MISC_GP_OBSDATA_0 0x81c +#define PADCTL_SNPS_OC_MAP 0xC +#define CONTROLLER_OC(inst, x) (((x) & 0x7) << (3 * (inst))) +#define CONTROLLER_OC_P0(x) (((x) & 0x7) << 0) +#define CONTROLLER_OC_P1(x) (((x) & 0x7) << 3) +#define CONTROLLER_OC_P2(x) (((x) & 0x7) << 6) + +#define PADCTL_OC_DET 0x18 +#define ENABLE0_OC_MAP(x) (((x) & 0x7) << 10) +#define ENABLE1_OC_MAP(x) (((x) & 0x7) << 13) + /* ULPI GPIO */ #define ULPI_STP TEGRA_GPIO_PY3 #define ULPI_DIR TEGRA_GPIO_PY1 @@ -1465,6 +1475,9 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; +#ifdef CONFIG_ARCH_TEGRA_11x_SOC + void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE); +#endif struct tegra_utmi_config *config = &phy->pdata->u_cfg.utmi; PHY_DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -1592,6 +1605,20 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) utmip_powerup_pmc_wake_detect(phy); phy->phy_clk_on = true; phy->hw_accessible = true; + +#ifdef CONFIG_ARCH_TEGRA_11x_SOC + val = readl(padctl_base + PADCTL_SNPS_OC_MAP); + val |= CONTROLLER_OC(phy->inst, 0x4); + writel(val, padctl_base + PADCTL_SNPS_OC_MAP); + + val = readl(padctl_base + PADCTL_OC_DET); + if (phy->inst == 0) + val |= ENABLE0_OC_MAP(config->vbus_oc_map); + if (phy->inst == 2) + val |= ENABLE1_OC_MAP(config->vbus_oc_map); + writel(val, padctl_base + PADCTL_OC_DET); +#endif + PHY_DBG("%s(%d) End inst:[%d]\n", __func__, __LINE__, phy->inst); return 0; } @@ -2201,6 +2228,9 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; +#ifdef CONFIG_ARCH_TEGRA_11x_SOC + void __iomem *padctl_base = IO_ADDRESS(TEGRA_XUSB_PADCTL_BASE); +#endif DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -2330,6 +2360,12 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) writel(val, base + USB_TXFILLTUNING); } +#ifdef CONFIG_ARCH_TEGRA_11x_SOC + val = readl(padctl_base + PADCTL_SNPS_OC_MAP); + val |= CONTROLLER_OC(phy->inst, 0x7); + writel(val, padctl_base + PADCTL_SNPS_OC_MAP); +#endif + return 0; } |