diff options
| author | Krishna Sitaraman <ksitaraman@nvidia.com> | 2014-02-27 19:01:14 -0800 |
|---|---|---|
| committer | Chao Xu <cxu@nvidia.com> | 2014-03-04 17:54:56 -0800 |
| commit | dc83402450605c918a045415cc86c4f32044cfc8 (patch) | |
| tree | 8f1ca3f5025583847ee11f39e54dcf7fbe4ad96f /arch/arm/mach-tegra/tegra12_clocks.c | |
| parent | d3306037ad55e317aed9013a1624beb386a6fec3 (diff) | |
ARM: T132: dvfs: Update cldvfs table v4
Add PLLX based table for A01 and
CLDVFS based table for A02
Change-Id: Ibbec5b5d0dc9b43f6e4447791675a7226c732419
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/375803
Reviewed-by: Chao Xu <cxu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra12_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_clocks.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c index f092cf9d7a62..f25064bf7d91 100644 --- a/arch/arm/mach-tegra/tegra12_clocks.c +++ b/arch/arm/mach-tegra/tegra12_clocks.c @@ -30,6 +30,7 @@ #include <linux/syscore_ops.h> #include <linux/platform_device.h> #include <linux/tegra-soc.h> +#include <linux/tegra-fuse.h> #include <asm/clkdev.h> @@ -4316,8 +4317,13 @@ static void __init tegra12_dfll_cpu_late_init(struct clk *c) ret = tegra_init_cl_dvfs(); if (!ret) { c->state = OFF; - if (tegra_platform_is_silicon()) + if (tegra_platform_is_silicon()) { use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE; +#ifdef CONFIG_ARCH_TEGRA_13x_SOC + if (tegra_cpu_speedo_id() == 0) + use_dfll = 0; +#endif + } tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll); tegra_cl_dvfs_debug_init(c); pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n", use_dfll); |