diff options
| author | Matt Wagner <mwagner@nvidia.com> | 2011-04-05 17:17:38 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:01 -0800 |
| commit | 1f828538e7cb3b17bdcc1851091eabc5026d0eb9 (patch) | |
| tree | 2fc8670f0511d5ec0c3c76a43715929202f23774 /arch/arm/mach-tegra/tegra2_clocks.c | |
| parent | 4139a6c3b43f17fec6caf30d3b58c2c584c775be (diff) | |
ARM: tegra: Limit host1x clock for AP20 SKUs
This changes the max frequency of the host1x clock to 108Mhz as in K32
in order to allow core voltage drop to 1000mV.
Bug 779576
Original-Change-Id: I71b6eff72462a32da5b4e622dbb6fe5032b2b7e6
Reviewed-on: http://git-master/r/24851
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R950b165f2075ea3ce64f3128ea1ac7b14e10a405
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index d94f7b125502..6e2960452e38 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2404,6 +2404,8 @@ static struct tegra_sku_rate_limit sku_limits[] = RATE_LIMIT("vde", 240000000, 0x04, 0x7, 0x08, 0x0F, 0x10), RATE_LIMIT("3d", 300000000, 0x04, 0x7, 0x08, 0x0F, 0x10), + RATE_LIMIT("host1x", 108000000, 0x0F), + RATE_LIMIT("sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("hclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("avp.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), |