diff options
| author | Tom Cherry <tcherry@nvidia.com> | 2011-03-21 15:10:00 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:41:59 -0800 |
| commit | 9875946e2190ae213b0b03c6612c929593568337 (patch) | |
| tree | b78ed3d5ba2bcc55c204891b996e73d14b4aa356 /arch/arm/mach-tegra/tegra2_clocks.c | |
| parent | ac10844665c7179c4e8f27415fb3aef7d7352bce (diff) | |
ARM: tegra: clock: Make dsi clock's parent plld_out0
Original-Change-Id: Ic9f248b692a2cf7069a39473f0d9ed8266c04ffe
Reviewed-on: http://git-master/r/23748
Tested-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R8de86d50b4968215c6ac5e14bf137fb1b7d1f38e
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 8c1c45e36167..de7df107b6b3 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2102,8 +2102,8 @@ static struct clk_mux_sel mux_pllp_out3[] = { { 0, 0}, }; -static struct clk_mux_sel mux_plld[] = { - { .input = &tegra_pll_d, .value = 0}, +static struct clk_mux_sel mux_plld_out0[] = { + { .input = &tegra_pll_d_out0, .value = 0}, { 0, 0}, }; @@ -2222,7 +2222,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 0x31E, 480000000, mux_clk_m, 0), /* requires min voltage */ PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 0x31E, 480000000, mux_clk_m, 0), /* requires min voltage */ PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 0x31E, 480000000, mux_clk_m, 0), /* requires min voltage */ - PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 0x31E, 500000000, mux_plld, 0), /* scales with voltage */ + PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 0x31E, 500000000, mux_plld_out0, 0), /* scales with voltage */ PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 0x31E, 72000000, mux_pllp_out3, 0), PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 0x31E, 150000000, mux_clk_m, 0), /* same frequency as VI */ PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 0x31E, 150000000, mux_clk_m, PERIPH_NO_RESET), |