diff options
author | Scott Williams <scwilliams@nvidia.com> | 2012-02-13 17:51:06 -0800 |
---|---|---|
committer | Simone Willett <swillett@nvidia.com> | 2012-02-15 15:41:44 -0800 |
commit | 0b042c720db13bbd042dace487e2e918386a45d4 (patch) | |
tree | 47cb5b5b3040c68aa71ea7dcf40645735e65dc75 /arch/arm/mach-tegra/tegra2_clocks.c | |
parent | 54c4f5a5a87c2ea56f4b2677fe22dde39e6918b3 (diff) |
ARM: tegra: clocks: Consolidate input frequency measurements
Consolidate the functions used to measure the input frequency
into a single implementation and perform the measurement only
once.
Change-Id: I3d13e608a7256d154373542ca001cbda9c03c21b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/83613
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
-rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 30 |
1 files changed, 1 insertions, 29 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index a3d0585dff0d..e526c4c46e2e 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -59,13 +59,6 @@ #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) -#define OSC_FREQ_DET 0x58 -#define OSC_FREQ_DET_TRIG (1<<31) - -#define OSC_FREQ_DET_STATUS 0x5C -#define OSC_FREQ_DET_BUSY (1<<31) -#define OSC_FREQ_DET_CNT_MASK 0xFFFF - #define PERIPH_CLK_SOURCE_I2S1 0x100 #define PERIPH_CLK_SOURCE_EMC 0x19c #define PERIPH_CLK_SOURCE_OSC 0x1fc @@ -190,27 +183,6 @@ static int tegra_periph_clk_enable_refcount[3 * 32]; #define chipid_readl() \ __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV) -unsigned long clk_measure_input_freq(void) -{ - u32 clock_autodetect; - clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); - do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); - clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); - if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { - return 12000000; - } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { - return 13000000; - } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { - return 19200000; - } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { - return 26000000; - } else { - pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect); - BUG(); - return 0; - } -} - static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate) { s64 divider_u71 = parent_rate * 2; @@ -253,7 +225,7 @@ static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c) { u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK; - c->rate = clk_measure_input_freq(); + c->rate = tegra_clk_measure_input_freq(); switch (c->rate) { case 12000000: auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; |