diff options
author | Bo Kim <bok@nvidia.com> | 2011-08-17 15:52:12 +0900 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:44 -0800 |
commit | 89514b46d0d26ac2821d8154997846d626a5bb17 (patch) | |
tree | 0ea2cc7d39f4408b946ebcd2abeba4e3bc1175bb /arch/arm/mach-tegra/tegra2_clocks.c | |
parent | 083c362fba0021213cba5dd417e0288a86c8a892 (diff) |
ARM: tegra: clock: tegra2_pll_clk_set_rate() process p field is greater then 2.
This change makes tegra2_pll_clk_set_rate() will process for p field is greater
then 2. It helps to increase VCO.
Bug 852217
Bug 842032
Reviewed-on: http://git-master/r/47492
(cherry picked from commit e1fefd8a7fb9751ddfad95e469666f3c876123a8)
Original-Change-Id: Id49b33cd8e568c6e5b619988a148242a85867eca
Reviewed-on: http://git-master/r/49585
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bo Kim <bok@nvidia.com>
Tested-by: Bo Kim <bok@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R0b4910e4265303f70b7c449d79c9c3ea8a67aa6d
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
-rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index c1fce5d5894b..f90c13cfd9a2 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -790,13 +790,25 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) PLL_BASE_DIVM_MASK); val |= (sel->m << PLL_BASE_DIVM_SHIFT) | (sel->n << PLL_BASE_DIVN_SHIFT); - BUG_ON(sel->p < 1 || sel->p > 2); + BUG_ON(sel->p < 1 || sel->p > 128); if (c->flags & PLLU) { if (sel->p == 1) val |= PLLU_BASE_POST_DIV; } else { if (sel->p == 2) val |= 1 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 4) + val |= 2 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 8) + val |= 3 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 16) + val |= 4 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 32) + val |= 5 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 64) + val |= 6 << PLL_BASE_DIVP_SHIFT; + else if (sel->p == 128) + val |= 7 << PLL_BASE_DIVP_SHIFT; } clk_writel(val, c->reg + PLL_BASE); |