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authorPrashant Gaikwad <pgaikwad@nvidia.com>2011-05-12 09:44:45 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:42:43 -0800
commitcbb71973b3a6882596bfb6dc7a181c5ce4f27a63 (patch)
tree0e1a76a90f7b1231a03864cbe481805f879c8383 /arch/arm/mach-tegra/tegra2_clocks.c
parent07fc331f7ca9eb8b6c4958cafb302b0e9def78bd (diff)
ARM: tegra: clocks: sku limit for pclk
sclk max rate for AP25 is 300MHz and pclk is set as 1:2 to sclk. pclk max rate changed to 150MHz for AP25. Bug 821534 Reviewed-on: http://git-master/r/31311 (cherry picked from commit 3655e9a4940bfa39ba103903f2e2f1d5f0cf7e2d) Original-Change-Id: Id10c322892e646c2c1f74cbf36268608fc268493 Reviewed-on: http://git-master/r/32874 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R7b21164fa84f78febf445ce4b60e92b1d70c6406
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 72b3ab578aa5..1bef372c5a8b 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2468,6 +2468,7 @@ static struct tegra_sku_rate_limit sku_limits[] =
RATE_LIMIT("sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
RATE_LIMIT("virt_sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
RATE_LIMIT("hclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+ RATE_LIMIT("pclk", 150000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
RATE_LIMIT("avp.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
RATE_LIMIT("bsea.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
RATE_LIMIT("vde", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),