diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2012-03-12 23:02:59 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:51:36 -0700 |
| commit | 0cd724c618ce2a9eacff8a04426191c821f9baf1 (patch) | |
| tree | 0d4cc4e6a76f364ecbd5ea100a22790f36453595 /arch/arm/mach-tegra/tegra2_clocks.c | |
| parent | 69c388c6862b14a62875b43b9b1400f33d0815af (diff) | |
ARM: tegra: clock: Entry for spi-sclk clock control
Tegra's spi requires some minimum sclk clock frequency for
proper functioning.
Making entry for spi-sclk clock so that spi driver can get the
proper clock for controlling the minimum rate of sclk.
bug 949393
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89524
(cherry picked from commit 542cbe457b1b19b8fdf8cbf193e38a00027060c2)
Change-Id: I3f829b36b1b42bb8b1c6e4e21745855e113c17c1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90294
Reviewed-by: Automatic_Commit_Validation_User
Rebase-Id: Rfcfa869cb1e7d14b1796992a41c20a1038cc4572
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 09fc5a9ec1bf..6e64375dd5ab 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2401,10 +2401,10 @@ static struct clk tegra_list_periph_clks[] = { PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 0x31E, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 0x31E, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 0x31E, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc1", "spi_tegra.0", "spi", 41, 0x134, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc2", "spi_tegra.1", "spi", 44, 0x118, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc3", "spi_tegra.2", "spi", 46, 0x11c, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc4", "spi_tegra.3", "spi", 68, 0x1b4, 0x31E, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 0x31E, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 0x31E, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 0x31E, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), @@ -2469,6 +2469,10 @@ static struct clk tegra_list_shared_clks[] = { SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_virtual_sclk), SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_virtual_sclk), SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_virtual_sclk), + SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_virtual_sclk), + SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_virtual_sclk), + SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_virtual_sclk), + SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_virtual_sclk), SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc), SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc), SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc), |