diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-05-12 09:44:45 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2012-03-22 23:26:05 -0700 |
| commit | 9510ebcf67a1af74907fe58252aab5d2903e900a (patch) | |
| tree | 2d2e0415d2510a272d2d143940e80aec7b36db80 /arch/arm/mach-tegra/tegra2_clocks.c | |
| parent | bedafdc823b546a2a1fe98fa0110f908f5955160 (diff) | |
ARM: tegra: clocks: sku limit for pclk
sclk max rate for AP25 is 300MHz and pclk is set as 1:2 to sclk.
pclk max rate changed to 150MHz for AP25.
Bug 821534
Reviewed-on: http://git-master/r/31311
(cherry picked from commit 3655e9a4940bfa39ba103903f2e2f1d5f0cf7e2d)
Original-Change-Id: Id10c322892e646c2c1f74cbf36268608fc268493
Reviewed-on: http://git-master/r/32874
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: R7b21164fa84f78febf445ce4b60e92b1d70c6406
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 9a3d8b66ee01..4fe2c3a3423e 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2473,6 +2473,7 @@ static struct tegra_sku_rate_limit sku_limits[] = RATE_LIMIT("sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("virt_sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("hclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), + RATE_LIMIT("pclk", 150000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("avp.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("bsea.sclk", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("vde", 300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), |