diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-06-08 14:43:35 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-07-16 20:13:27 -0700 |
| commit | 0f64d5820ea1caa2b879aea7f68614d45edf6d32 (patch) | |
| tree | 838833a7ee6b013bd5a872969b51ff4af98b0a53 /arch/arm/mach-tegra/tegra3_clocks.c | |
| parent | 9aed57c5b382154e89bb08ca160a413162e0e17d (diff) | |
ARM: tegra: dvfs: Update Tegra3 sdmmc dvfs tables
Added Tegra3 sdmmc4 dvfs table and downgraded sdmmc 2/4 maximum
clock limits based on recent characterization results.
Bug 817679
Bug 841336
Change-Id: I88ddeaabf0739efc0f9c18c41cace331792d4d43
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107780
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 1161f1ca64f9..122d9d51580c 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -4322,9 +4322,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ - PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 50000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ - PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), |