diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-03-01 15:20:40 -0800 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-07-23 17:34:19 -0700 |
| commit | 3a50dd6e2b0183e9189ab746296d9ff6398fb86d (patch) | |
| tree | 0c9a7a45c43d9d8b9c753f8e2f3b7d695f3a4e7a /arch/arm/mach-tegra/tegra3_clocks.c | |
| parent | 8615a322ddf8c836579c56aabb0c56c891d9849c (diff) | |
ARM: tegra: clock: Set SCLK floor for CPU mode switch
Set SCLK floor to 80MHz for Tegra3 CPU mode switch.
Bug 933984
Change-Id: Ibbb0a24cd763c11b3cead60efe26096bae3e6ddd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/106035
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
Tested-by: Jay Cheng <jacheng@nvidia.com>
(cherry picked from commit 842f7ddb7a188e36a2ff153dc0d8ed38b5e28319)
Reviewed-on: http://git-master/r/113981
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 87592e2ee3c5..9344a84cf62a 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -319,6 +319,7 @@ static int tegra3_emc_relock_set_rate(struct clk *emc, unsigned long old_rate, static unsigned long cpu_stay_on_backup_max; static struct clk *emc_bridge; +static struct clk *cpu_mode_sclk; static bool detach_shared_bus; module_param(detach_shared_bus, bool, 0644); @@ -1050,6 +1051,8 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP : TEGRA_POWER_CLUSTER_G; + clk_enable(cpu_mode_sclk); /* set SCLK floor for cluster switch */ + /* Since in both LP and G mode CPU main and backup sources are the same, set rate on the new parent just synchronizes super-clock muxes before mode switch with no PLL re-locking */ @@ -1057,6 +1060,7 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) if (ret) { pr_err("%s: Failed to set rate %lu for %s\n", __func__, rate, p->name); + clk_disable(cpu_mode_sclk); return ret; } @@ -1072,6 +1076,7 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) clk_disable(p); pr_err("%s: Failed to switch %s mode to %s\n", __func__, c->name, p->name); + clk_disable(cpu_mode_sclk); return ret; } @@ -1080,6 +1085,7 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) clk_disable(c->parent); clk_reparent(c, p); + clk_disable(cpu_mode_sclk); return 0; } @@ -4403,7 +4409,8 @@ struct clk tegra_list_clks[] = { SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), - SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("cpu_mode.sclk","cpu_mode", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0), @@ -5393,6 +5400,7 @@ void __init tegra_soc_init_clocks(void) tegra3_init_one_clock(&tegra_clk_out_list[i]); emc_bridge = &tegra_clk_emc_bridge; + cpu_mode_sclk = tegra_get_clock_by_name("cpu_mode.sclk"); /* Initialize to default */ tegra_init_cpu_edp_limits(0); |