diff options
| author | Amit Kamath <akamath@nvidia.com> | 2012-04-02 17:22:57 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-04-03 17:56:22 -0700 |
| commit | 3b693812e9c606561b92d665d2eb676616e27ac4 (patch) | |
| tree | ec335468249e867d26e2a67bee34800d92fc02d2 /arch/arm/mach-tegra/tegra3_clocks.c | |
| parent | b867f4986fd0952a6614e098ccfefcbf3aef5b2a (diff) | |
arm: tegra3: change min_rate for sclk
Change the minimal rate of sclk to 12 MHz and set the lowest
frequency of sbus to be 40 MHz when display is on.
bug 939415
Original change http://git-master/r/#change,76959
Change-Id: I81cda6a95494764721c1be5b4001c476f3aed6ab
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/93850
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 0b2d4f4fc6d6..0bceeeb9469f 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3958,7 +3958,7 @@ static struct clk tegra_clk_pclk = { .reg_shift = 0, .ops = &tegra_bus_ops, .max_rate = 167000000, - .min_rate = 40000000, + .min_rate = 12000000, }; static struct raw_notifier_head sbus_rate_change_nh; @@ -4301,6 +4301,7 @@ struct clk tegra_list_clks[] = { SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0), SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0), |