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| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2012-01-03 15:48:45 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-01-06 17:05:11 +0530 |
| commit | 1e60bd6ec86b65ba77c43cfa133c651b13b22caa (patch) | |
| tree | d71365db8f447985b52fea6ae1e41bed24e7477c /arch/arm/mach-tegra/tegra3_dvfs.c | |
| parent | 5c44a3f0e7e7fc3b00c6d58921b322174b328152 (diff) | |
ARM: tegra: power: L2 cache sync only for CPU0 LP2
Bug 922010
Change-Id: I19724ae5d8421b2fccfc604ecb0a867d20fddf75
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/72986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_dvfs.c')
0 files changed, 0 insertions, 0 deletions