ARM: tegra: clock: Add Tegra3 0.95V core voltage step

- Expanded Tegra3 DVFS tables with 0.95V core voltage step
- Updated cbus minimum rate calculation, since cbus can not
  run at 0.95V
- Updated PLLM dvfs initialization, since PLLM can no longer
  be voltage independent, even when its usage is restricted.

Bug 817679
Bug 841336

Change-Id: I4973dc19d351ce237f2b249ebf75a79abf3afef4
Reviewed-on: http://git-master/r/74141
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76463
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 136 insertions, 112 deletions

diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 8f560ca6f7b9..8497fceed22f 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -38,8 +38,8 @@ static const int cpu_millivolts[MAX_DVFS_FREQS] = {
 static const unsigned int cpu_cold_offs_mhz[MAX_DVFS_FREQS] = {
 	  50,  50,  50,  50,  50,  50,  50,  50,  50,   50,   50,   50,   50,   50,   50,   50,   50,   50};
 
-static const int core_millivolts[MAX_DVFS_FREQS] =
-	{1000, 1050, 1100, 1150, 1200, 1250, 1300};
+static const int core_millivolts[MAX_DVFS_FREQS] = {
+	950, 1000, 1050, 1100, 1150, 1200, 1250, 1300};
 
 #define KHZ 1000
 #define MHZ 1000000
@@ -62,7 +62,7 @@ static struct dvfs_rail tegra3_dvfs_rail_vdd_cpu = {
 static struct dvfs_rail tegra3_dvfs_rail_vdd_core = {
 	.reg_id = "vdd_core",
 	.max_millivolts = 1300,
-	.min_millivolts = 1000,
+	.min_millivolts = 950,
 	.step = VDD_SAFE_STEP,
 };
 
@@ -74,7 +74,7 @@ static struct dvfs_rail *tegra3_dvfs_rails[] = {
 static int tegra3_get_core_floor_mv(int cpu_mv)
 {
 	if (cpu_mv < 850)
-		return 1000;
+		return  950;
 	if (cpu_mv < 1000)
 		return 1100;
 	if ((tegra_cpu_speedo_id() < 2) ||
@@ -203,101 +203,122 @@ static struct dvfs cpu_dvfs_table[] = {
 	}
 
 static struct dvfs core_dvfs_table[] = {
-	/* Core voltages (mV):		   1000,   1050,   1100,   1150,    1200,    1250,    1300 */
+	/* Core voltages (mV):		    950,   1000,   1050,   1100,   1150,    1200,    1250,    1300 */
 	/* Clock limits for internal blocks, PLLs */
-	CORE_DVFS("cpu_lp", 0, 1, KHZ,   294000, 342000, 427000, 475000,  500000,  500000,  500000),
-	CORE_DVFS("cpu_lp", 1, 1, KHZ,   294000, 342000, 427000, 475000,  500000,  500000,  500000),
-	CORE_DVFS("cpu_lp", 2, 1, KHZ,   295000, 370000, 428000, 475000,  513000,  579000,  620000),
-	CORE_DVFS("cpu_lp", 3, 1, KHZ,        1,      1,      1,      1,       1,  450000,  450000),
-
-	CORE_DVFS("emc",    0, 1, KHZ,   266500, 266500, 266500, 266500,  533000,  533000,  533000),
-	CORE_DVFS("emc",    1, 1, KHZ,   408000, 408000, 408000, 408000,  667000,  667000,  667000),
-	CORE_DVFS("emc",    2, 1, KHZ,   408000, 408000, 408000, 408000,  667000,  667000,  800000),
-	CORE_DVFS("emc",    3, 1, KHZ,        1,      1,      1,      1,       1,  625000,  625000),
-
-	CORE_DVFS("sbus",   0, 1, KHZ,   136000, 164000, 191000, 216000,  216000,  216000,  216000),
-	CORE_DVFS("sbus",   1, 1, KHZ,   205000, 205000, 227000, 227000,  267000,  267000,  267000),
-	CORE_DVFS("sbus",   2, 1, KHZ,   205000, 205000, 227000, 227000,  267000,  334000,  334000),
-	CORE_DVFS("sbus",   3, 1, KHZ,        1,      1,      1,      1,       1,  216000,  216000),
-
-	CORE_DVFS("vi",     0, 1, KHZ,   216000, 285000, 300000, 300000,  300000,  300000,  300000),
-	CORE_DVFS("vi",     1, 1, KHZ,   216000, 267000, 300000, 371000,  409000,  409000,  409000),
-	CORE_DVFS("vi",     2, 1, KHZ,   219000, 267000, 300000, 371000,  409000,  425000,  425000),
-	CORE_DVFS("vi",     3, 1, KHZ,        1,      1,      1,      1,       1,  300000,  300000),
-
-	CORE_DVFS("vde",    0, 1, KHZ,   228000, 275000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("mpe",    0, 1, KHZ,   234000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("2d",     0, 1, KHZ,   267000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("epp",    0, 1, KHZ,   267000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("3d",     0, 1, KHZ,   234000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("3d2",    0, 1, KHZ,   234000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("se",     0, 1, KHZ,   267000, 285000, 332000, 380000,  416000,  416000,  416000),
-
-	CORE_DVFS("vde",    1, 1, KHZ,   228000, 275000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("mpe",    1, 1, KHZ,   234000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("2d",     1, 1, KHZ,   267000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("epp",    1, 1, KHZ,   267000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("3d",     1, 1, KHZ,   234000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("3d2",    1, 1, KHZ,   234000, 285000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("se",     1, 1, KHZ,   267000, 285000, 332000, 380000,  416000,  416000,  416000),
-
-	CORE_DVFS("vde",    2, 1, KHZ,   247000, 304000, 352000, 400000,  437000,  484000,  520000),
-	CORE_DVFS("mpe",    2, 1, KHZ,   247000, 304000, 361000, 408000,  446000,  484000,  520000),
-	CORE_DVFS("2d",     2, 1, KHZ,   267000, 304000, 361000, 408000,  446000,  484000,  520000),
-	CORE_DVFS("epp",    2, 1, KHZ,   267000, 304000, 361000, 408000,  446000,  484000,  520000),
-	CORE_DVFS("3d",     2, 1, KHZ,   247000, 304000, 361000, 408000,  446000,  484000,  520000),
-	CORE_DVFS("3d2",    2, 1, KHZ,   247000, 304000, 361000, 408000,  446000,  484000,  520000),
-	CORE_DVFS("se",     2, 1, KHZ,   267000, 304000, 361000, 408000,  446000,  484000,  520000),
-
-	CORE_DVFS("vde",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
-	CORE_DVFS("mpe",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
-	CORE_DVFS("2d",     3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
-	CORE_DVFS("epp",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
-	CORE_DVFS("3d",     3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
-	CORE_DVFS("3d2",    3, 1, KHZ,        1,      1,      1,      1,       1,  484000,  484000),
-	CORE_DVFS("se",     3, 1, KHZ,        1,      1,      1,      1,       1,  650000,  650000),
-
-	CORE_DVFS("host1x", 0, 1, KHZ,   152000, 188000, 222000, 254000,  267000,  267000,  267000),
-	CORE_DVFS("host1x", 1, 1, KHZ,   152000, 188000, 222000, 254000,  267000,  267000,  267000),
-	CORE_DVFS("host1x", 2, 1, KHZ,   152000, 188000, 222000, 254000,  267000,  267000,  267000),
-	CORE_DVFS("host1x", 3, 1, KHZ,        1,      1,      1,      1,       1,  300000,  300000),
-
-	CORE_DVFS("cbus",   0, 1, KHZ,   228000, 275000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("cbus",   1, 1, KHZ,   228000, 275000, 332000, 380000,  416000,  416000,  416000),
-	CORE_DVFS("cbus",   2, 1, KHZ,   247000, 304000, 352000, 400000,  437000,  484000,  520000),
-	CORE_DVFS("cbus",   3, 1, KHZ,   484000, 484000, 484000, 484000,  484000,  484000,  484000),
-
-	CORE_DVFS("pll_c",  -1, 1, KHZ,  667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
-	CORE_DVFS("pll_m",  -1, 1, KHZ,  667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
-
-	/* Core voltages (mV):		   1000,   1050,   1100,   1150,    1200,   1250,    1300 */
+	CORE_DVFS("cpu_lp", 0, 1, KHZ,        1, 294000, 342000, 427000, 475000,  500000,  500000,  500000),
+	CORE_DVFS("cpu_lp", 1, 1, KHZ,   204000, 294000, 342000, 427000, 475000,  500000,  500000,  500000),
+	CORE_DVFS("cpu_lp", 2, 1, KHZ,   204000, 295000, 370000, 428000, 475000,  513000,  579000,  620000),
+	CORE_DVFS("cpu_lp", 3, 1, KHZ,        1,      1,      1,      1,      1,       1,  450000,  450000),
+
+	CORE_DVFS("emc",    0, 1, KHZ,        1, 266500, 266500, 266500, 266500,  533000,  533000,  533000),
+	CORE_DVFS("emc",    1, 1, KHZ,   102000, 408000, 408000, 408000, 408000,  667000,  667000,  667000),
+	CORE_DVFS("emc",    2, 1, KHZ,   102000, 408000, 408000, 408000, 408000,  667000,  667000,  800000),
+	CORE_DVFS("emc",    3, 1, KHZ,        1,      1,      1,      1,      1,       1,  625000,  625000),
+
+	CORE_DVFS("sbus",   0, 1, KHZ,        1, 136000, 164000, 191000, 216000,  216000,  216000,  216000),
+	CORE_DVFS("sbus",   1, 1, KHZ,    51000, 205000, 205000, 227000, 227000,  267000,  267000,  267000),
+	CORE_DVFS("sbus",   2, 1, KHZ,    51000, 205000, 205000, 227000, 227000,  267000,  334000,  334000),
+	CORE_DVFS("sbus",   3, 1, KHZ,        1,      1,      1,      1,      1,       1,  216000,  216000),
+
+	CORE_DVFS("vi",     0, 1, KHZ,        1, 216000, 285000, 300000, 300000,  300000,  300000,  300000),
+	CORE_DVFS("vi",     1, 1, KHZ,        1, 216000, 267000, 300000, 371000,  409000,  409000,  409000),
+	CORE_DVFS("vi",     2, 1, KHZ,        1, 219000, 267000, 300000, 371000,  409000,  425000,  425000),
+	CORE_DVFS("vi",     3, 1, KHZ,        1,      1,      1,      1,      1,       1,  300000,  300000),
+
+	CORE_DVFS("vde",    0, 1, KHZ,        1, 228000, 275000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("mpe",    0, 1, KHZ,        1, 234000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("2d",     0, 1, KHZ,        1, 267000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("epp",    0, 1, KHZ,        1, 267000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("3d",     0, 1, KHZ,        1, 234000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("3d2",    0, 1, KHZ,        1, 234000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("se",     0, 1, KHZ,        1, 267000, 285000, 332000, 380000,  416000,  416000,  416000),
+
+	CORE_DVFS("vde",    1, 1, KHZ,        1, 228000, 275000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("mpe",    1, 1, KHZ,        1, 234000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("2d",     1, 1, KHZ,        1, 267000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("epp",    1, 1, KHZ,        1, 267000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("3d",     1, 1, KHZ,        1, 234000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("3d2",    1, 1, KHZ,        1, 234000, 285000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("se",     1, 1, KHZ,        1, 267000, 285000, 332000, 380000,  416000,  416000,  416000),
+
+	CORE_DVFS("vde",    2, 1, KHZ,        1, 247000, 304000, 352000, 400000,  437000,  484000,  520000),
+	CORE_DVFS("mpe",    2, 1, KHZ,        1, 247000, 304000, 361000, 408000,  446000,  484000,  520000),
+	CORE_DVFS("2d",     2, 1, KHZ,        1, 267000, 304000, 361000, 408000,  446000,  484000,  520000),
+	CORE_DVFS("epp",    2, 1, KHZ,        1, 267000, 304000, 361000, 408000,  446000,  484000,  520000),
+	CORE_DVFS("3d",     2, 1, KHZ,        1, 247000, 304000, 361000, 408000,  446000,  484000,  520000),
+	CORE_DVFS("3d2",    2, 1, KHZ,        1, 247000, 304000, 361000, 408000,  446000,  484000,  520000),
+	CORE_DVFS("se",     2, 1, KHZ,        1, 267000, 304000, 361000, 408000,  446000,  484000,  520000),
+
+	CORE_DVFS("vde",    3, 1, KHZ,        1,      1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("mpe",    3, 1, KHZ,        1,      1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("2d",     3, 1, KHZ,        1,      1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("epp",    3, 1, KHZ,        1,      1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("3d",     3, 1, KHZ,        1,      1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("3d2",    3, 1, KHZ,        1,      1,      1,      1,      1,       1,  484000,  484000),
+	CORE_DVFS("se",     3, 1, KHZ,        1,      1,      1,      1,      1,       1,  650000,  650000),
+
+	CORE_DVFS("host1x", 0, 1, KHZ,        1, 152000, 188000, 222000, 254000,  267000,  267000,  267000),
+	CORE_DVFS("host1x", 1, 1, KHZ,        1, 152000, 188000, 222000, 254000,  267000,  267000,  267000),
+	CORE_DVFS("host1x", 2, 1, KHZ,        1, 152000, 188000, 222000, 254000,  267000,  267000,  267000),
+	CORE_DVFS("host1x", 3, 1, KHZ,        1,      1,      1,      1,      1,       1,  300000,  300000),
+
+	CORE_DVFS("cbus",   0, 1, KHZ,        1, 228000, 275000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("cbus",   1, 1, KHZ,        1, 228000, 275000, 332000, 380000,  416000,  416000,  416000),
+	CORE_DVFS("cbus",   2, 1, KHZ,        1, 247000, 304000, 352000, 400000,  437000,  484000,  520000),
+	CORE_DVFS("cbus",   3, 1, KHZ,        1, 484000, 484000, 484000, 484000,  484000,  484000,  484000),
+
+	CORE_DVFS("pll_c",  -1, 1, KHZ,  533000, 667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
+
+	/*
+	 * PLLM dvfs is common across all speedo IDs with one special exception
+	 * for T30 and T33, rev A02+, provided PLLM usage is restricted. Both
+	 * common and restricted table are included, and table selection is
+	 * handled by is_pllm_dvfs() below.
+	 */
+	CORE_DVFS("pll_m",  -1, 1, KHZ,  533000, 667000, 667000, 800000, 800000, 1066000, 1066000, 1066000),
+#ifdef CONFIG_TEGRA_PLLM_RESTRICTED
+	CORE_DVFS("pll_m",   2, 1, KHZ,  533000, 800000, 800000, 800000, 800000, 1066000, 1066000, 1066000),
+#endif
+	/* Core voltages (mV):		    950,   1000,   1050,   1100,   1150,   1200,    1250,     1300 */
 	/* Clock limits for I/O peripherals */
-	CORE_DVFS("mipi",   0, 1, KHZ,        1,      1,      1,      1,      1,       1,        1),
-	CORE_DVFS("mipi",   1, 1, KHZ,        1,      1,      1,      1,  60000,   60000,    60000),
-	CORE_DVFS("mipi",   2, 1, KHZ,        1,      1,      1,      1,  60000,   60000,    60000),
-	CORE_DVFS("mipi",   3, 1, KHZ,        1,      1,      1,      1,      1,       1,        1),
-
-	CORE_DVFS("fuse_burn", -1, 1, KHZ,    1,      1,      1,  26000,  26000,   26000,    26000),
-	CORE_DVFS("sdmmc1",-1, 1, KHZ,   104000, 104000, 104000, 104000, 208000,  208000,   208000),
-	CORE_DVFS("sdmmc3",-1, 1, KHZ,   104000, 104000, 104000, 104000, 208000,  208000,   208000),
-	CORE_DVFS("ndflash", -1, 1, KHZ, 120000, 120000, 120000, 200000, 200000,  200000,   200000),
-
-	CORE_DVFS("nor",    0, 1, KHZ,   115000, 130000, 130000, 133000, 133000,  133000,   133000),
-	CORE_DVFS("nor",    1, 1, KHZ,   115000, 130000, 130000, 133000, 133000,  133000,   133000),
-	CORE_DVFS("nor",    2, 1, KHZ,   115000, 130000, 130000, 133000, 133000,  133000,   133000),
-	CORE_DVFS("nor",    3, 1, KHZ,        1,      1,      1,      1,      1,  108000,   108000),
-
-	CORE_DVFS("sbc1",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
-	CORE_DVFS("sbc2",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
-	CORE_DVFS("sbc3",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
-	CORE_DVFS("sbc4",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
-	CORE_DVFS("sbc5",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
-	CORE_DVFS("sbc6",  -1, 1, KHZ,    40000,  60000,  60000,  60000, 100000,  100000,   100000),
-
-	CORE_DVFS("tvo",   -1, 1, KHZ,        1, 297000, 297000, 297000, 297000,  297000,   297000),
-	CORE_DVFS("cve",   -1, 1, KHZ,        1, 297000, 297000, 297000, 297000,  297000,   297000),
-	CORE_DVFS("dsia",  -1, 1, KHZ,   275000, 275000, 275000, 275000, 275000,  275000,   275000),
-	CORE_DVFS("dsib",  -1, 1, KHZ,   275000, 275000, 275000, 275000, 275000,  275000,   275000),
+	CORE_DVFS("mipi",   0, 1, KHZ,        1,      1,      1,      1,      1,      1,       1,        1),
+	CORE_DVFS("mipi",   1, 1, KHZ,        1,      1,      1,      1,      1,  60000,   60000,    60000),
+	CORE_DVFS("mipi",   2, 1, KHZ,        1,      1,      1,      1,      1,  60000,   60000,    60000),
+	CORE_DVFS("mipi",   3, 1, KHZ,        1,      1,      1,      1,      1,      1,       1,        1),
+
+	CORE_DVFS("fuse_burn", -1, 1, KHZ,    1,      1,      1,      1,  26000,  26000,   26000,    26000),
+	CORE_DVFS("sdmmc1", -1, 1, KHZ,  104000, 104000, 104000, 104000, 104000, 208000,  208000,   208000),
+	CORE_DVFS("sdmmc3", -1, 1, KHZ,  104000, 104000, 104000, 104000, 104000, 208000,  208000,   208000),
+	CORE_DVFS("ndflash", -1, 1, KHZ,      1, 120000, 120000, 120000, 200000, 200000,  200000,   200000),
+
+	CORE_DVFS("nor",    0, 1, KHZ,        1, 115000, 130000, 130000, 133000, 133000,  133000,   133000),
+	CORE_DVFS("nor",    1, 1, KHZ,        1, 115000, 130000, 130000, 133000, 133000,  133000,   133000),
+	CORE_DVFS("nor",    2, 1, KHZ,        1, 115000, 130000, 130000, 133000, 133000,  133000,   133000),
+	CORE_DVFS("nor",    3, 1, KHZ,        1,      1,      1,      1,      1,      1,  108000,   108000),
+
+	CORE_DVFS("sbc1",  -1, 1, KHZ,        1,  52000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc2",  -1, 1, KHZ,        1,  52000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc3",  -1, 1, KHZ,        1,  52000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc4",  -1, 1, KHZ,        1,  52000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc5",  -1, 1, KHZ,        1,  52000,  60000,  60000,  60000, 100000,  100000,   100000),
+	CORE_DVFS("sbc6",  -1, 1, KHZ,        1,  52000,  60000,  60000,  60000, 100000,  100000,   100000),
+
+	CORE_DVFS("usbd",  -1, 1, KHZ,        1, 480000, 480000, 480000, 480000, 480000,  480000,   480000),
+	CORE_DVFS("usb2",  -1, 1, KHZ,        1, 480000, 480000, 480000, 480000, 480000,  480000,   480000),
+	CORE_DVFS("usb3",  -1, 1, KHZ,        1, 480000, 480000, 480000, 480000, 480000,  480000,   480000),
+
+	CORE_DVFS("sata",  -1, 1, KHZ,        1, 216000, 216000, 216000, 216000, 216000,  216000,   216000),
+	CORE_DVFS("sata_oob", -1, 1, KHZ,     1, 216000, 216000, 216000, 216000, 216000,  216000,   216000),
+	CORE_DVFS("pcie",  -1, 1, KHZ,        1, 250000, 250000, 250000, 250000, 250000,  250000,   250000),
+	CORE_DVFS("afi",   -1, 1, KHZ,        1, 250000, 250000, 250000, 250000, 250000,  250000,   250000),
+	CORE_DVFS("pll_e", -1, 1, KHZ,        1, 100000, 100000, 100000, 100000, 100000,  100000,   100000),
+
+	CORE_DVFS("tvdac", -1, 1, KHZ,        1, 220000, 220000, 220000, 220000, 220000,  220000,   220000),
+	CORE_DVFS("tvo",   -1, 1, KHZ,        1,      1, 297000, 297000, 297000, 297000,  297000,   297000),
+	CORE_DVFS("cve",   -1, 1, KHZ,        1,      1, 297000, 297000, 297000, 297000,  297000,   297000),
+	CORE_DVFS("dsia",  -1, 1, KHZ,        1, 275000, 275000, 275000, 275000, 275000,  275000,   275000),
+	CORE_DVFS("dsib",  -1, 1, KHZ,        1, 275000, 275000, 275000, 275000, 275000,  275000,   275000),
+	CORE_DVFS("hdmi",  -1, 1, KHZ,        1, 148500, 148500, 148500, 148500, 148500,  148500,   148500),
 
 	/*
 	 * The clock rate for the display controllers that determines the
@@ -305,15 +326,18 @@ static struct dvfs core_dvfs_table[] = {
 	 * to the display block.  Disable auto-dvfs on the display clocks,
 	 * and let the display driver call tegra_dvfs_set_rate manually
 	 */
-	CORE_DVFS("disp1",  0, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
-	CORE_DVFS("disp1",  1, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
-	CORE_DVFS("disp1",  2, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
-	CORE_DVFS("disp1",  3, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
-
-	CORE_DVFS("disp2",  0, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
-	CORE_DVFS("disp2",  1, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
-	CORE_DVFS("disp2",  2, 0, KHZ,   151000, 268000, 268000, 268000, 268000,  268000,   268000),
-	CORE_DVFS("disp2",  3, 0, KHZ,   120000, 120000, 120000, 120000, 190000,  190000,   190000),
+	CORE_DVFS("disp1",  0, 0, KHZ,        1, 120000, 120000, 120000, 120000, 190000,  190000,   190000),
+	CORE_DVFS("disp1",  1, 0, KHZ,        1, 151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp1",  2, 0, KHZ,        1, 151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp1",  3, 0, KHZ,        1, 120000, 120000, 120000, 120000, 190000,  190000,   190000),
+
+	CORE_DVFS("disp2",  0, 0, KHZ,        1, 120000, 120000, 120000, 120000, 190000,  190000,   190000),
+	CORE_DVFS("disp2",  1, 0, KHZ,        1, 151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp2",  2, 0, KHZ,        1, 151000, 268000, 268000, 268000, 268000,  268000,   268000),
+	CORE_DVFS("disp2",  3, 0, KHZ,        1, 120000, 120000, 120000, 120000, 190000,  190000,   190000),
+
+	CORE_DVFS("pwm",   -1, 1, KHZ,        1, 408000, 408000, 408000, 408000, 408000,  408000,   408000),
+	CORE_DVFS("spdif_out", -1, 1, KHZ,    1,  26000,  26000,  26000,  26000,  26000,   26000,    26000),
 };
 
 
@@ -372,11 +396,11 @@ module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops,
 static bool __init is_pllm_dvfs(struct clk *c, struct dvfs *d)
 {
 #ifdef CONFIG_TEGRA_PLLM_RESTRICTED
-	/* Restricting PLLM usage on T30 and T33, rev A02+, allows to apply
-	   maximum PLLM frequency to clock tree at minimum core voltage;
-	   no need to enable dvfs on PLLM in this case */
-	if ((tegra_cpu_speedo_id() == 2) || (tegra_cpu_speedo_id() == 5))
-	   return false;
+	/* Do not apply common PLLM dvfs table on T30 and T33, rev A02+ and
+	   do not apply restricted PLLM dvfs table for other SKUs/revs */
+	if (((tegra_cpu_speedo_id() == 2) || (tegra_cpu_speedo_id() == 5)) ==
+	    (d->speedo_id == -1))
+		return false;
 #endif
 	/* Check if PLLM boot frequency can be applied to clock tree at
 	   minimum voltage. If yes, no need to enable dvfs on PLLM */
@@ -888,7 +912,7 @@ static int __init init_core_cap_one(struct clk *c, unsigned long *freqs)
 
 		if (rate == 0) {
 			rate = next_rate;
-			pr_warn("tegra3_dvfs: minimum %s cap %lu requires"
+			pr_warn("tegra3_dvfs: minimum %s rate %lu requires"
 				" %d mV", c->name, rate, next_v);
 		}
 		freqs[i] = rate;