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authorAlex Frid <afrid@nvidia.com>2011-11-10 22:51:20 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:50:19 -0800
commit3abec30416ae0a8561b75270bb0c6287e0935cf3 (patch)
treeca7dc12e22e982e00f2c0215fbb01938fc7c2917 /arch/arm/mach-tegra/tegra3_dvfs.c
parente6fa3337de9a8d0ee7236f424905d7ccdcc2401e (diff)
ARM: tegra: dvfs: Update Tegra3 x3 CPU DVFS tables
Bug 841336 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 459a539b413bc34fa6bed54cc363b4a6ffbaff59) (cherry picked from commit 470c3c4fad40a570dedfd51a52577fd4c91c5269) Change-Id: I63214eaa437345bf7657f4c53a6dd73473e1e532 Reviewed-on: http://git-master/r/66513 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R9e3e92e6c27da3c8760b01cda223463c75d6d16f
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_dvfs.c')
-rw-r--r--arch/arm/mach-tegra/tegra3_dvfs.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 2ad2c90629f9..7b66952727fb 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -165,8 +165,11 @@ static struct dvfs cpu_dvfs_table[] = {
CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 720, 720, 880, 880, 880, 1090, 1180, 1200, 1300, 1310, 1380, 1400, 1500),
CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1500),
- CPU_DVFS("cpu_g", 5, 3, MHZ, 1, 1, 1, 1, 1, 1, 1, 1180, 1230, 1300, 1320, 1350, 1380, 1420, 1450, 1450, 1700),
- CPU_DVFS("cpu_g", 6, 3, MHZ, 1, 1, 1, 1, 1, 1, 1, 1180, 1230, 1300, 1320, 1350, 1380, 1420, 1450, 1450, 1700),
+ CPU_DVFS("cpu_g", 5, 3, MHZ, 1, 1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1470, 1500, 1540, 1700),
+ CPU_DVFS("cpu_g", 5, 4, MHZ, 1, 1, 840, 840, 1000, 1000, 1000, 1200, 1280, 1330, 1380, 1400, 1480, 1500, 1520, 1700),
+
+ CPU_DVFS("cpu_g", 6, 3, MHZ, 1, 1, 800, 800, 1000, 1000, 1000, 1180, 1230, 1300, 1330, 1380, 1400, 1470, 1500, 1540, 1700),
+ CPU_DVFS("cpu_g", 6, 4, MHZ, 1, 1, 840, 840, 1000, 1000, 1000, 1200, 1280, 1330, 1380, 1400, 1480, 1500, 1520, 1700),
/*
* "Safe entry" to be used when no match for chip speedo, process