diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-06-08 13:30:09 -0700 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-06-14 07:43:43 -0700 |
| commit | 7152262b92cb8ad4a75a494efc9d6c14fb260000 (patch) | |
| tree | dec7b499aebe2addcdcd1b07c76583e65c6c6c20 /arch/arm/mach-tegra/tegra3_dvfs.c | |
| parent | 8cf8ac01d862f1630d25c1cba465453b6fe0ff5b (diff) | |
ARM: tegra: dvfs: Update Tegra3 display subsystem dvfs tables
Updated 0.95V entries in Tegra3 dvfs tables for display and dsi
with recent characterization results. Removed hdmi and crt dvfs
since characterization allows running these modules at max rate
in the entire supported voltage range.
Bug 817679
Bug 841336
Change-Id: I28651a692e30a20536613460ea0e45155a530af7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/107778
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_dvfs.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 6574c8ad025e..d3965c040d6a 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -329,12 +329,10 @@ static struct dvfs core_dvfs_table[] = { CORE_DVFS("afi", -1, 1, KHZ, 1, 250000, 250000, 250000, 250000, 250000, 250000, 250000, 250000), CORE_DVFS("pll_e", -1, 1, KHZ, 1, 100000, 100000, 100000, 100000, 100000, 100000, 100000, 100000), - CORE_DVFS("tvdac", -1, 1, KHZ, 1, 220000, 220000, 220000, 220000, 220000, 220000, 220000, 220000), CORE_DVFS("tvo", -1, 1, KHZ, 1, 1, 297000, 297000, 297000, 297000, 297000, 297000, 297000), CORE_DVFS("cve", -1, 1, KHZ, 1, 1, 297000, 297000, 297000, 297000, 297000, 297000, 297000), - CORE_DVFS("dsia", -1, 1, KHZ, 1, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000), - CORE_DVFS("dsib", -1, 1, KHZ, 1, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000), - CORE_DVFS("hdmi", -1, 1, KHZ, 1, 148500, 148500, 148500, 148500, 148500, 148500, 148500, 148500), + CORE_DVFS("dsia", -1, 1, KHZ, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000), + CORE_DVFS("dsib", -1, 1, KHZ, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000, 275000), /* * The clock rate for the display controllers that determines the @@ -343,13 +341,13 @@ static struct dvfs core_dvfs_table[] = { * and let the display driver call tegra_dvfs_set_rate manually */ CORE_DVFS("disp1", 0, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000), - CORE_DVFS("disp1", 1, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), - CORE_DVFS("disp1", 2, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), + CORE_DVFS("disp1", 1, 0, KHZ, 155000, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), + CORE_DVFS("disp1", 2, 0, KHZ, 155000, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), CORE_DVFS("disp1", 3, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000), CORE_DVFS("disp2", 0, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000), - CORE_DVFS("disp2", 1, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), - CORE_DVFS("disp2", 2, 0, KHZ, 1, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), + CORE_DVFS("disp2", 1, 0, KHZ, 155000, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), + CORE_DVFS("disp2", 2, 0, KHZ, 155000, 155000, 268000, 268000, 268000, 268000, 268000, 268000, 268000), CORE_DVFS("disp2", 3, 0, KHZ, 1, 120000, 120000, 120000, 120000, 190000, 190000, 190000, 190000), CORE_DVFS("pwm", -1, 1, KHZ, 1, 408000, 408000, 408000, 408000, 408000, 408000, 408000, 408000), |