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authorAlex Frid <afrid@nvidia.com>2012-01-23 13:40:48 -0800
committerRohan Somvanshi <rsomvanshi@nvidia.com>2012-02-03 05:43:19 -0800
commitd83fa39d946383ce6370441ee3ad00717f6a19c1 (patch)
treebb98361f77ebb196bd39803c86ee065965981f72 /arch/arm/mach-tegra/tegra3_dvfs.c
parent410f87783b83d27e0f8853c190c3ef5b851ad333 (diff)
ARM: tegra: dvfs: Add Tegra3 x7 CPU dvfs entries
Bug 841336 Reviewed-on: http://git-master/r/76912 Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-on: http://git-master/r/78706 Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_dvfs.c')
-rw-r--r--arch/arm/mach-tegra/tegra3_dvfs.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 8497fceed22f..d4fa2488f780 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -183,6 +183,12 @@ static struct dvfs cpu_dvfs_table[] = {
CPU_DVFS("cpu_g", 10, -1, MHZ, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900),
CPU_DVFS("cpu_g", 11, -1, MHZ, 1, 1, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600),
+ CPU_DVFS("cpu_g", 12, 3, MHZ, 1, 1, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700),
+ CPU_DVFS("cpu_g", 12, 4, MHZ, 1, 1, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700),
+
+ CPU_DVFS("cpu_g", 13, 3, MHZ, 1, 1, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700),
+ CPU_DVFS("cpu_g", 13, 4, MHZ, 1, 1, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700),
+
/*
* "Safe entry" to be used when no match for chip speedo, process
* corner is found (just to boot at low rate); must be the last one
@@ -396,9 +402,10 @@ module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops,
static bool __init is_pllm_dvfs(struct clk *c, struct dvfs *d)
{
#ifdef CONFIG_TEGRA_PLLM_RESTRICTED
- /* Do not apply common PLLM dvfs table on T30 and T33, rev A02+ and
+ /* Do not apply common PLLM dvfs table on T30, T33, T37 rev A02+ and
do not apply restricted PLLM dvfs table for other SKUs/revs */
- if (((tegra_cpu_speedo_id() == 2) || (tegra_cpu_speedo_id() == 5)) ==
+ int cpu = tegra_cpu_speedo_id();
+ if (((cpu == 2) || (cpu == 5) || (cpu == 13)) ==
(d->speedo_id == -1))
return false;
#endif